Intel
®
8 Series / C220 Series Chipset
Family Platform Controller Hub
(PCH)
Datasheet
June 2013
328904-001
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death.
SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND
ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL
CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT
LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS
SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or
characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice.
Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-
4725, or go to: http://www.intel.com/design/literature.htm.
Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release.
Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or
services and any such use of Intel's internal code names is at the sole risk of the user.
I
2
C is a two-wire communications bus/protocol developed by NXP. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including NXP Semiconductors N.V.
Intel
®
Anti-Theft Technology (Intel
®
AT): No system can provide absolute security under all conditions. Requires an enabled chipset, BIOS, firmware and
software and a subscription with a capable Service Provider. Consult your System manufacturer and Service Provider for availability and functionality.
Intel assumes no liability for lost or stolen data and/or systems or any other damages resulting thereof. For more information, visit http://
www.intel.com/go/anti-theft
Intel
®
High Definition Audio (Intel
®
HD Audio): Requires an Intel
®
HD Audio enabled system. Consult your PC manufacturer for more information. Sound
quality will depend on equipment and actual implementation. For more information about Intel
®
HD Audio, refer to http://www.intel.com/design/
chipsets/hdaudio.htm
Intel
®
Trusted Execution Technology (Intel
®
TXT): No computer system can provide absolute security under all conditions. Intel
®
TXT requires a
computer system with Intel
®
Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT
compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT
requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses. For more information, see
http://www.intel.com/technology/security
Intel
®
Active Management Technology (Intel
®
AMT) requires activation and a system with a corporate network connection, an Intel
®
AMT-enabled
chipset, network hardware and software. For notebooks, Intel AMT may be unavailable or limited over a host OS-based VPN, when connecting wirelessly,
on battery power, sleeping, hibernating or powered off. Results dependent upon hardware, setup & configuration. For more information, visit http://
www.intel.com/technology/platform-technology/intel-amt
No computer system can provide absolute security under all conditions. Intel
®
Trusted Execution Technology (Intel
®
TXT) requires a computer system
with Intel
®
Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible Measured
Launched Environment (MLE). Intel TXT also requires the system to contain a TPM v1.s. For more information, visit http://www.intel.com/technology/
security
Intel
®
Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM). Functionality,
performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all
operating systems. Consult your PC manufacturer. For more information, visit http://www.intel.com/go/virtualization.
Intel
®
vPro™ Technology is sophisticated and requires setup and activation. Availability of features and results will depend upon the setup and
configuration of your hardware, software and IT environment. To learn more visit: http://www.intel.com/technology/vpro
Intel, Intel vPro, Xeon, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2013, Intel Corporation. All rights reserved.
2
Datasheet
Contents
1
Introduction
............................................................................................................ 43
1.1
About This Manual ............................................................................................. 43
1.1.1
Chapter Descriptions ............................................................................. 44
1.2
Overview ......................................................................................................... 46
1.2.1
Capability Overview............................................................................... 47
®
1.3
Intel 8 Series / C220 Series Chipset Family SKU Definition.................................... 54
1.4
Device and Revision ID Table .............................................................................. 60
Signal Description
................................................................................................... 63
2.1
Flexible I/O ...................................................................................................... 65
2.2
USB Interface ................................................................................................... 66
2.3
PCI Express* .................................................................................................... 70
2.4
Serial ATA Interface........................................................................................... 72
2.5
Clock Signals .................................................................................................... 75
2.6
Real Time Clock Interface ................................................................................... 77
2.7
External RTC Circuitry ........................................................................................ 77
2.8
Interrupt Interface ............................................................................................ 78
2.9
Processor Interface............................................................................................ 78
2.10 Direct Media Interface (DMI) to Host Controller ..................................................... 79
2.11 Intel
®
Flexible Display Interface (Intel
®
FDI) ........................................................ 79
2.12 Analog Display / VGA DAC Signals ....................................................................... 80
2.13 Digital Display Signals........................................................................................ 81
2.14 Embedded DisplayPort* (eDP*) Backlight Control Signals ....................................... 81
2.15 Intel
®
High Definition Audio (Intel
®
HD Audio) Link ............................................... 82
2.16 Low Pin Count (LPC) Interface............................................................................. 83
2.17 General Purpose I/O Signals ............................................................................... 83
2.18 Functional Straps .............................................................................................. 91
2.19 SMBus Interface................................................................................................ 95
2.20 System Management Interface............................................................................ 95
2.21 Controller Link .................................................................................................. 96
2.22 Serial Peripheral Interface (SPI) .......................................................................... 96
2.23 Manageability Signals ........................................................................................ 98
2.24 Power Management Interface.............................................................................. 99
2.25 Power and Ground Signals ................................................................................ 103
2.26 Thermal Signals .............................................................................................. 104
2.27 Miscellaneous Signals ...................................................................................... 105
2.28 Testability Signals ........................................................................................... 106
2.29 Reserved / Test Pins ........................................................................................ 107
PCH Pin States.......................................................................................................
109
3.1
Integrated Pull-Ups and Pull-Downs ................................................................... 109
3.2
Output Signals Planes and States ...................................................................... 112
3.3
Input and I/O Signals Planes and States............................................................. 118
PCH and System Clocks
......................................................................................... 125
4.1
Straps Related to Clock Configuration ................................................................ 125
4.2
Platform Clocking Requirements ........................................................................ 126
4.3
Functional Blocks ............................................................................................ 127
4.4
Clock Configuration Access Overview ................................................................. 130
4.5
Integrated Clock Controller (ICC) Registers......................................................... 130
4.5.1
ICC Registers under Intel
®
Management Engine (Intel
®
ME) Control.......... 130
4.5.1.1
SSCDIVINTPHASE_DMI100—100MHz DMI Clock SSC Divider
Integer Phase Control Register................................................ 131
4.5.1.2
SSCTRIPARAM_DMI100—100MHz DMI Clock SSC Triangle
Register............................................................................... 131
4.5.1.3
SSCCTL_DMI100—100MHz DMI Clock SSC Control Register ........ 131
4.5.1.4
SSCDIVINTPHASE_PCHPCIE100—100MHz PCH PCIE Clock SSC
Divider Integer Phase Register................................................ 132
4.5.1.5
SSCTRIPARAM_PCHPCIE100—100MHz PCH PCIE Clock SSC
Triangle Register................................................................... 132
4.5.1.6
SSCCTL_PCHPCIE100—100MHz PCH PCIE* Clock SSC Control
Register............................................................................... 132
2
3
4
Datasheet
3
4.5.1.7
4.5.1.8
4.5.1.9
4.5.1.10
4.5.1.11
4.5.1.12
4.5.1.13
4.5.1.14
4.5.1.15
4.5.1.16
4.5.1.17
4.5.1.18
4.5.1.19
5
DIV_PCI33—33MHz Single Ended Clock Divide and Spread
Enable Register ..................................................................... 132
DIV_FLEX4824—48MHz and 24MHz Single Ended FLEX Clock
Divide Enable Register ........................................................... 133
OCKEN—Output Clock Enable Register...................................... 134
SEFLXBP—Single Ended Flex Buffer Parameter Register .............. 136
SEPCICLKBP—Single Ended 33 MHz Clock Buffer
Parameter Register ................................................................ 137
DCOSS—Differential Clock Out Source Select Register ................ 138
SECOSS—Single Ended Clock Out Source Select Register ............ 139
MCSS—Miscellaneous Clock Source Select Register .................... 140
PLLRCS—PLL Reference Clock Select Register ............................ 140
ICCCTL—ICC Control Register ................................................. 140
PMPCI—33MHz Single Ended Clock Power Management Register .. 141
PM1PCIECLK—Power Management 1 PCIE Clock Register ............ 142
PM2PCIECLK—Power Management 2 PCIE Clock Register ............ 145
Functional Description
........................................................................................... 149
5.1
Flexible I/O..................................................................................................... 149
5.2
PCI-to-PCI Bridge ............................................................................................ 150
5.2.1
PCI Bus Interface ................................................................................ 150
5.2.2
PCI Legacy Mode ................................................................................. 150
5.3
PCI Express* Root Ports (D28:F0~F7) ................................................................ 151
5.3.1
Supported PCIe* Port Configurations...................................................... 151
5.3.2
Interrupt Generation ............................................................................ 151
5.3.3
Power Management ............................................................................. 152
5.3.3.1
S3/S4/S5 Support ................................................................. 152
5.3.3.2
Resuming from Suspended State ............................................. 152
5.3.3.3
Device Initiated PM_PME Message............................................ 152
5.3.3.4
SMI/SCI Generation............................................................... 153
5.3.3.5
Latency Tolerance Reporting (LTR) .......................................... 153
5.3.3.6
Opportunistic Buffer Flush/Fill (OBFF)....................................... 153
5.3.4
SERR# Generation............................................................................... 153
5.3.5
Hot-Plug............................................................................................. 154
5.3.5.1
Presence Detection ................................................................ 154
5.3.5.2
Message Generation .............................................................. 154
5.3.5.3
Attention Button Detection...................................................... 155
5.3.5.4
SMI/SCI Generation............................................................... 155
5.4
Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 156
5.4.1
GbE PCI Express* Bus Interface ............................................................ 159
5.4.1.1
Transaction Layer .................................................................. 159
5.4.1.2
Data Alignment ..................................................................... 159
5.4.1.3
Configuration Request Retry Status.......................................... 159
5.4.2
Error Events and Error Reporting ........................................................... 159
5.4.2.1
Data Parity Error ................................................................... 159
5.4.2.2
Completion with Unsuccessful Completion Status ....................... 160
5.4.3
Ethernet Interface ............................................................................... 160
5.4.3.1
Intel
®
Ethernet Network Connection I127LM/V Platform LAN
Connect Device Interface........................................................ 160
5.4.4
PCI Power Management........................................................................ 161
5.4.4.1
Wake Up .............................................................................. 161
5.4.5
Configurable LEDs ............................................................................... 163
5.4.6
Function Level Reset Support (FLR)........................................................ 164
5.4.6.1
FLR Steps............................................................................. 164
5.5
Low Pin Count (LPC) Bridge (with System and
Management Functions) (D31:F0) ...................................................................... 165
5.5.1
LPC Interface ...................................................................................... 165
5.5.1.1
LPC Cycle Types .................................................................... 165
5.5.1.2
Start Field Definition .............................................................. 166
5.5.1.3
Cycle Type / Direction (CYCTYPE + DIR) ................................... 166
5.5.1.4
Size..................................................................................... 167
5.5.1.5
SYNC ................................................................................... 167
5.5.1.6
SYNC Time-Out ..................................................................... 167
5.5.1.7
SYNC Error Indication ............................................................ 168
5.5.1.8
LFRAME# Usage .................................................................... 168
5.5.1.9
I/O Cycles ............................................................................ 168
5.5.1.10 Bus Master Cycles ................................................................. 168
4
Datasheet
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.5.1.11 LPC Power Management......................................................... 168
5.5.1.12 Configuration and PCH Implications ......................................... 169
DMA Operation (D31:F0) .................................................................................. 170
5.6.1
Channel Priority .................................................................................. 170
5.6.1.1
Fixed Priority ........................................................................ 170
5.6.1.2
Rotating Priority.................................................................... 171
5.6.2
Address Compatibility Mode.................................................................. 171
5.6.3
Summary of DMA Transfer Sizes ........................................................... 171
5.6.3.1
Address Shifting When Programmed for 16-Bit I/O Count
by Words ............................................................................. 171
5.6.4
Autoinitialize ...................................................................................... 172
5.6.5
Software Commands ........................................................................... 172
Low Pin Count (LPC) DMA ................................................................................. 173
5.7.1
Asserting DMA Requests ...................................................................... 173
5.7.2
Abandoning DMA Requests ................................................................... 174
5.7.3
General Flow of DMA Transfers ............................................................. 174
5.7.4
Terminal Count ................................................................................... 174
5.7.5
Verify Mode........................................................................................ 175
5.7.6
DMA Request De-assertion ................................................................... 175
5.7.7
SYNC Field / LDRQ# Rules.................................................................... 176
8254 Timers (D31:F0) ..................................................................................... 176
5.8.1
Timer Programming............................................................................. 177
5.8.2
Reading from the Interval Timer ........................................................... 178
5.8.2.1
Simple Read......................................................................... 178
5.8.2.2
Counter Latch Command........................................................ 178
5.8.2.3
Read Back Command............................................................. 178
8259 Programmable Interrupt Controllers (PIC) (D31:F0) ..................................... 179
5.9.1
Interrupt Handling............................................................................... 180
5.9.1.1
Generating Interrupts ............................................................ 180
5.9.1.2
Acknowledging Interrupts....................................................... 181
5.9.1.3
Hardware/Software Interrupt Sequence ................................... 181
5.9.2
Initialization Command Words (ICWx).................................................... 182
5.9.2.1
ICW1 .................................................................................. 182
5.9.2.2
ICW2 .................................................................................. 182
5.9.2.3
ICW3 .................................................................................. 182
5.9.2.4
ICW4 .................................................................................. 182
5.9.3
Operation Command Words (OCW)........................................................ 183
5.9.4
Modes of Operation ............................................................................. 183
5.9.4.1
Fully Nested Mode................................................................. 183
5.9.4.2
Special Fully-Nested Mode...................................................... 183
5.9.4.3
Automatic Rotation Mode (Equal Priority Devices)...................... 183
5.9.4.4
Specific Rotation Mode (Specific Priority).................................. 184
5.9.4.5
Poll Mode ............................................................................. 184
5.9.4.6
Edge and Level Triggered Mode............................................... 184
5.9.4.7
End of Interrupt (EOI) Operations ........................................... 184
5.9.4.8
Normal End of Interrupt ......................................................... 184
5.9.4.9
Automatic End of Interrupt Mode............................................. 185
5.9.5
Masking Interrupts .............................................................................. 185
5.9.5.1
Masking on an Individual Interrupt Request .............................. 185
5.9.5.2
Special Mask Mode ................................................................ 185
5.9.6
Steering PCI Interrupts ........................................................................ 185
Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 186
5.10.1 Interrupt Handling............................................................................... 186
5.10.2 Interrupt Mapping ............................................................................... 186
5.10.3 PCI / PCI Express* Message-Based Interrupts......................................... 187
5.10.4 IOxAPIC Address Remapping ................................................................ 187
5.10.5 External Interrupt Controller Support..................................................... 187
Serial Interrupt (D31:F0) ................................................................................. 188
5.11.1 Start Frame........................................................................................ 188
5.11.2 Data Frames ...................................................................................... 189
5.11.3 Stop Frame ........................................................................................ 189
5.11.4 Specific Interrupts Not Supported Using SERIRQ ..................................... 189
5.11.5 Data Frame Format ............................................................................. 190
Real Time Clock (D31:F0)................................................................................. 191
5.12.1 Update Cycles..................................................................................... 191
5.12.2 Interrupts .......................................................................................... 192
5.12.3 Lockable RAM Ranges .......................................................................... 192
Datasheet
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
