SST26WF064C
1.8V, 64 Mbit Serial Quad I/O (SQI) Flash Memory
Features
• Single Voltage Read and Write Operations
- 1.65-1.95V
• Serial Interface Architecture
- Mode 0 and Mode 3
- Nibble-wide multiplexed I/O’s with SPI-like serial
command structure
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
- Dual-Transfer Rate (DTR) Operation
• High Speed Clock Frequency
- 104 MHz max
- 54 MHz max (DTR)
• Burst Modes
- Continuous linear burst
- 8/16/32/64 Byte linear burst with wrap-around
• Superior Reliability
- Endurance: 100,000 Cycles (min)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby current: 10 µA (typical)
- Deep Power-Down current: 2.5 µA (typical)
• Fast Erase Time
- Sector/Block Erase: 18 ms (typ), 25 ms (max)
- Chip Erase: 35 ms (typ), 50 ms (max)
• Page-Program
- 256 Bytes per page in x1 or x4 mode
• End-of-Write Detection
- Software polling the BUSY bit in status register
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Four 8 KByte top and bottom parameter overlay
blocks
- One 32 KByte top and bottom overlay block
- Uniform 64 KByte overlay blocks
• Write-Suspend
- Suspend Program or Erase operation to access
another block/sector
• Software Reset (RST) mode
• Hardware Reset Pin
• Supports JEDEC-compliant Serial Flash Discov-
erable Parameter (SFDP) table
• Software Protection
- Individual-Block Write Protection with permanent
lock-down capability
- 64 KByte blocks, two 32 KByte blocks, and
eight 8 KByte parameter blocks
- Read Protection on top and bottom 8 KByte
parameter blocks
• Security ID
- One-Time Programmable (OTP) 2 KByte,
Secure ID
- 64 bit unique, factory pre-programmed identifier
- User-programmable area
• Temperature Range
- Industrial: -40°C to +85°C
• Packages Available
- 8-contact WDFN (6mm x 5mm)
- 8-lead SOIJ (5.28 mm)
- 16-lead SOIC (7.50 mm)
- 24-ball TBGA (8mm x 6mm)
• All devices are RoHS compliant
Product Description
The Serial Quad I/O™ (SQI™) family of flash-memory
devices features a six-wire, 4-bit I/O interface that
allows for low-power, high-performance operation in a
low pin-count package. The SST26WF064C also sup-
ports full command-set compatibility to traditional Serial
Peripheral Interface (SPI) protocol. System designs
using SQI flash devices occupy less board space and
ultimately lower system costs.
All members of the 26 Series, SQI family are manufac-
tured with proprietary, high-performance CMOS Super-
Flash
®
technology. The split-gate cell design and thick-
oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
The SST26WF064C significantly improves performance
and reliability, while lowering power consumption. These
devices write (Program or Erase) with a single power sup-
ply of 1.65-1.95V. The total energy consumed is a function
of the applied voltage, current, and time of application. For
any given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time.
Therefore, the total energy consumed during any Erase or
Program operation is less than alternative flash memory
technologies.
2016-2017 Microchip Technology Inc.
Preliminary
DS20005430B-page 1
SST26WF064C
The SST26WF064C is offered in 8-contact WDFN
(6 mm x 5 mm), 8-lead SOIJ (5.28 mm), 16-lead SOIC
(7.50 mm), and 24-ball TBGA (8mm x 6mm) packages.
See
Figure 2-1
for pin assignments.
The following configuration is available upon order:
• SST26WF064C default at power-up has the WP#
and RESET#/HOLD# pins enabled, with the SIO2
and SIO3 pins disabled, to initiate SPI-protocol.
See
“I/O Configuration (IOC)” on page 13
for more
information about configuring the WP#, RESET/
HOLD#, SIO2, and SIO3 pins.
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Most Current Data Sheet
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS20005430B-page 2
Preliminary
2016-2017 Microchip Technology Inc.
SST26WF064C
1.0
BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
FIGURE 1-1:
OTP
Address
Buffers
and
Latches
X - Decoder
SuperFlash
Memory
Y - Decoder
Control Logic
Page Buffer,
I/O Buffers
and
Data Latches
Serial Interface
WP# HOLD# SCK
CE#
SIO [3:0]
RESET#
20005430 B1.0
2016-2017 Microchip Technology Inc.
Preliminary
DS20005430B-page 3
SST26WF064C
2.0
PIN DESCRIPTION
PIN DESCRIPTIONS
CE#
SO/SIO1
WP#/SIO2
VSS
1
2
8
7
FIGURE 2-1:
VDD
RESET#
/HOLD#/SIO3
SCK
SI/SIO0
08-soic S2A P1.0
Top View
3
4
6
5
8-Lead SOIJ
CE#
SO/SIO1
WP#/SIO2
VSS
1
8
VDD
RESET#
/HOLD#/SIO3
2
7
Top View
3
6
8-Contact WDFN
SCK
SI/SIO0
08-wson QA P1.0
4
5
RESET#/
HOLD#/SIO3
VDD
RESET#
NC
NC
NC
CE#
SO/SIO1
Top View
SCK
SI/SIO0
NC
NC
NC
NC
VSS
WP#/SIO2
16-SOIC P1.0
16-lead SOIC
Top View
4
RESET# V
DD
3
NC
2
NC
1
NC
NC
NC
NC
NC
NC
SCK
CE#
S0/
SIO1
NC
NC
V
SS
NC
SI/
SIO0
NC
NC
WP#/
SIO2
RESET#/
HOLD#/
SIO3
NC
NC
24-Ball TBGA
A
B
C
D
E
F
T4D-P1.0
DS20005430B-page 4
Preliminary
2016-2017 Microchip Technology Inc.
SST26WF064C
TABLE 2-1:
Symbol
SCK
PIN DESCRIPTION
Pin Name
Serial Clock
Functions
Provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
Transfer commands, addresses, or data serially into the device or data out of
the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.
Transfer commands, addresses or data serially into the device. Inputs are
latched on the rising edge of the serial clock. SI is the default state after a
power on reset or hardware reset.
Transfer data serially out of the device. Data is shifted out on the falling edge of
the serial clock. SO is the default state after a power on reset or hardware reset.
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence; or in the case of Write operations,
for the command/data input sequence.
The WP# pin is used in conjunction with the WPEN and IOC bits in the configu-
ration register to prohibit Write operations to the Block-Protection register. This
pin only works in SPI, single-bit and dual-bit Read mode.
Temporarily stops serial communication with the SPI Flash memory while the
device is selected. This pin only works in SPI, single-bit and dual-bit Read
mode and must be tied high when not in use.
Reset the operation and internal logic of the device.
Provide power supply voltage.
SIO[3:0]
Serial Data
Input/Output
Serial Data Input
for SPI mode
Serial Data Output
for SPI mode
Chip Enable
SI
SO
CE#
WP#
Write Protect
HOLD#
RESET#
V
DD
V
SS
Hold
Reset
Power Supply
Ground
2016-2017 Microchip Technology Inc.
Preliminary
DS20005430B-page 5
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