USB3.0-IP FMC demo board Manual
[ Ver2.0E]
AB07-USB3FMC (2.5V I/O) or AB07-USB3FMC-1.8VIF (1.8V I/O)
Introduction
Thank you for choosing USB3.0-IP FMC demo board [Part Number:AB07-USB3FMC] (“demo board” in this
manual).
The demo board will connect with FPGA Evaluation board that furnishes FMC extension connector, so that
user can evaluate USB3.0-IP from DesignGateway. The demo board can be applicable to both USB3.0
Device-IP (Product number: USB3D-IPxxx) evaluation and Host-IP (Product number: USB3H-IPxxx)
evaluation.
Take enough care that FMC interface voltage of the demo board is fixed, so that user shall
never use any FPGA board that cannot adjust to proper FMC I/O voltage. Otherwise, FPGA board or
the demo board will be damaged!
User can try USB3.0 SuperSpeed real board operation by using FPGA board with this demo board and
bit-file for evaluation provided from DesignGateway.
The demo board mainly mounts following parts.
TUSB1310A (USB3.0 PHY device from T.I) and related power supply circuit.
A-type USB3.0 connector
FMC-LPC connector
The 1meter-length USB3.0 AtoA cable is attached with the demo board product. USB3.0 Device-IP core
(Product Name: USB3D-IPxxx) evaluation needs to use this USB3.0 cable. Note that USB3.0 AtoB cable is
not attached with the product, so that user needs to arrange USB3.0 AtoB cable to evaluate USB3.0 Host-IP
core (Product Name: USB3H-IPxxx).
Note that the demo board only supports SuperSpeed (5Gbps) communication and does not support
any legacy USB speed. (There is no DM/DP signal connection resource for USB2.0 or earlier standard)
because the demo board is dedicated to USB3.0-IP from DesignGateway only.
Package List
The demo board includes following items in its product.
●
USB3FMC board: 1pcs
●
USB3.0 AtoA cable: 1pcs.
(AtoA
cable is for Device-IP core evaluation)
Copyright©2011 Design Gateway Co,.Ltd. All rights reserved.
Page 1/5
Board Outline
The demo board size is 69mm width and 58.65mm length.
Following figure-1 shows board outline.
A-type USB3.0
Connector
JP1 Jumper
header
(*)
Power LED
TUSB1310A
(PHY device)
FMC-LPC connector on
solder side
Figure-1: AB07-USB3FMC board outline
Note(*):
JP1 Jumper header is to set short or open between 5V power supply from USB (VUSB) and
on-board 5V power supply output.
When evaluate Device-IP, do not set Jumper Socket
on JP1.
When evaluate Host-IP, set Jumper Socket
on JP1.
Copyright©2011 Design Gateway Co,.Ltd. All rights reserved.
Page 2/5
Pin Assignment
Pin assignment between FPGA I/O pin and TUSB1310 is listed following table-1. For
AB07-USB3FMC-1.8VIF, this board only supports 1.8V I/O so that it cannot connect with SP605 or ML605,
however, signal connection information between FMC pin and TUSB1310A is same as AB07-USB3FMC.
Demo Bd.FMC-LPC
FMC FMC definition
Pin#
C10
LA06_P
C11
LA06_N
C14
LA10_P
C15
LA10_N
C18
LA14_P
C19
LA14_N
C22
LA18_P_CC
C23
LA18_N_CC
C26
LA27_P
C27
LA27_N
D8
D9
D11
D12
D14
D15
D17
D18
D20
D21
D23
D24
D26
D27
LA01_P_CC
LA01_N_CC
LA05_P
LA05_N
LA09_P
LA09_N
LA13_P
LA13_N
LA17_P_CC
LA17_N_CC
LA23_P
LA23_N
LA26_P
LA26_N
TUSB1310A on Demo Bd
XC6SLX45 on SP-605
Chip
TUSB1310A
FPGA
Spartan-6
Pin#
signal name
PIN#
pin attribution
P2
TX_DATA4
D4
L2P_0
USB_PWEN
D5
L2N_0
M1
TX_DATA8
H10
L33P_0
F3
RX_ELECIDLE
H11
L33N_0
G2
TX_DATA15
C17
L50P_0
A17
L50N_0
C2
RX_DATA4
T12
L29P_GC_2
D3
RX_TERM
U12
L29N_GC_2
B4
RX_DATA10
AA10
L41P_2
AB10
L41N_2
P3
L11
N2
K11
M2
K3
H1
A6
B1
C7
A3
TX_DATA2
TX_DEEMPH0
TX_DATA5
TX_DEEMPH1
TX_DATA9
TX_ELECIDLE
TX_DATA13
PCLK
(GND)
RX_DATA5
RX_STATUS2
RX_DATA7
F14
F15
C4
A4
F7
F8
G16
F17
Y11
AB11
U9
V9
U14
U13
L36P_GC_0
L36N_GC_0
L6P_0
L6N_0
L7P_0
L7N_0
L51P_0
L51N_0
L32P_GC_2
L32N_GC_2
L50P_2
L50N_2
L16P_2
L16N_2
XC6VLX240 on ML-605
FPGA
Virtex-6
PIN#
pin attribution
K33
L16P_16
J34
L16N_16
F30
L3P_16
G30
L3N_16
C33
L6P_16
B34
L6N_16
L29
L11P_SC_15
L30
L11N_SC_15
R31
L14P_15
R32
L14N_15
F31
E31
H34
H33
L25
L26
D34
C34
N28
N29
R28
R27
L33
M32
L11P_SC_16
L11N_SC_16
L14P_16
L14N_16
L18P_16
L18N_16
L8P_SC_16
L8N_SC_16
L9P_MC_15
L9N_MC_15
L18P_15
L18N_15
L6P_15
L6N_15
Remark
Not used
Table-1:
Pin connection list
Copyright©2011 Design Gateway Co,.Ltd. All rights reserved.
Page 3/5
Demo Bd.FMC-LPC
FMC FMC definition
Pin#
G2
CLK1_M2C_P
G3
CLK1_M2C_N
G6
LA00_P_CC
G7
LA00_N_CC
G9
LA03_P
G10
LA03_N
G12
LA08_P
G13
LA08_N
G15
LA12_P
G16
LA12_N
G18
LA16_P
G19
LA16_N
G21
LA20_P
G22
LA20_N
G24
LA22_P
G25
LA22_N
G27
LA25_P
G28
LA25_N
G30
LA29_P
G31
LA29_N
G33
LA31_P
G34
LA31_N
G36
LA33_P
G37
LA33_N
H2
H4
H5
H7
H8
H10
H11
H13
H14
H16
H17
H19
H20
H22
H23
H25
H26
H28
H29
H31
H32
H34
H35
H37
H38
PRSNT
CLK0_M2C_P
CLK0_M2C_N
LA02_P
LA02_N
LA04_P
LA04_N
LA07_P
LA07_N
LA11_P
LA11_N
LA15_P
LA15_N
LA19_P
LA19_N
LA21_P
LA21_N
LA24_P
LA24_N
LA28_P
LA28_N
LA30_P
LA30_N
LA32_P
LA32_N
TUSB1310A on Demo Bd
XC6SLX45 on SP-605
Chip
TUSB1310A
FPGA
Spartan-6
Pin#
signal name
PIN#
pin attribution
E16
L37P_GC_0
F16
L37N_GC_0
P5
TX_DATA0
G9
L34P_GC_0
M6
TXDET_RXLPBK
F10
L34N_GC_0
N3
TX_DATA3
B18
L63P_0
M9
TX_MARGIN0
A18
L63N_0
P1
TX_DATA6
B20
L65P_0
J3
PHY_RESETN
A20
L65N_0
L2
TX_DATA10
H13
L38P_0
G3
POWER_DOWN1
G13
L38N_0
J2
TX_DATA12
C5
L8P_0
J1
TX_DATAK0
A5
L8N_0
D1
RX_DATA2
R9
L59P_2
F1
RX_VALID
R8
L59N_2
D2
RX_DATA1
V7
L58P_2
C5
RX_STATUS0
W8
L58N_2
A2
RX_DATA6
W14
L20P_2
C6
RX_STATUS1
Y14
L20N_2
A4
RX_DATA9
T15
L23P_2
B7
RX_DATAK1
U15
L23N_2
B8
RX_DATA12
U16
L4P_2
H11
PWRPRESENT
V15
L4N_2
B9
RX_DATA15
Y17
L15P_2
IPL_DD0
AB17
L15N_2
(GND)
Y16
H12
G11
G8
F9
C19
A19
B2
A2
H14
G15
D18
D19
R11
T11
V11
W11
AA14
AB14
AA16
AB16
Y15
AB15
W17
Y18
IO_L17P_2
L35P_GC_0
L35N_GC_0
L32P_0
L32N_0
L64P_0
L64N_0
L3P_0
L3N_0
L49P_0
L49N_0
L62P_0
L62N_0
L22P_2
L22N_2
L42P_2
L42N_2
L6P_2
L6N_2
L19P_2
L19N_2
L21P_2
L21N_2
L5P_2
L5N_2
XC6VLX240 on ML-605
FPGA
Virtex-6
PIN#
pin attribution
F33
L10P_MC_16
G33
L10N_MC_16
K26
L9P_MC_16
K27
L9N_MC_16
J31
L19P_16
J32
L19N_16
J30
L13P_16
K29
L13N_16
E32
L2P_16
E33
L2N_16
A33
L4P_16
B33
L4N_16
P29
L19P_15
R29
L19N_15
N27
L5P_15
P27
L5N_15
P31
L4P_15
P30
L4N_15
N34
L18P_15
P34
L18N_15
M31
L90P_15
L31
L90N_15
K32
L2P_15
K31
L2N_15
AD9
A10
B10
G31
H30
K28
J29
G32
H32
D31
D32
C32
B32
M30
N30
R26
T26
N32
P32
N33
M33
M26
M27
N25
M25
L14P_34
L1P_GC_34
L1N_GC_34
L5P_16
L5N_16
L7P_16
L7N_16
L17P_16
L17N_16
L15P_16
L15N_16
L0P_16
L0N_16
L17P_15
L17N_15
L15P_15
L15N_15
L8P_SC_15
L8N_SC_15
L10P_MC_15
L10N_MC_15
L3P_15
L3N_15
L1P_15
L1N_15
Remark
Not used
N4
J11
L3
L10
N1
H3
K1
H2
G1
E2
E3
C1
E3
B3
C8
B5
A7
A8
A9
TX_DATA1
RESETN
TX_DATA11
OUT_ENABLE
TX_DATA7
POWER_DOWN0
TX_CLK
(GND)
TX_DATA14
TX_DATAK1
RX_DATA0
PHY_STATUS
RX_DATA3
PHY_STATUS
RX_DATA8
RX_POLARITY
RX_DATA11
RX_DATAK0
RX_DATA13
USB_OVCR
RX_DATA14
IPL_DC0
Not used
Not used
Table-1:
Pin connection list (cont’d)
Copyright©2011 Design Gateway Co,.Ltd. All rights reserved.
Page 4/5
Disclaimer
The manufacturer of the product limits liability in following situation or use.
Any damage to the connected Host-PC via USB interface.
Any damage to the FPGA evaluation board or the demo board
when user mistakenly connect
AB07-USB3FMC with non-2.5V FMC I/F or AB07-USB3FMC-1.8VIF with non-1.8V FMC I/F.
Any misoperation in Device-IP evaluation when attached USB3.0 AtoA cable is not used.
Any misoperation in Host-IP evaluation when USB3.0 cable is not USB3.0 standard compliant.
DesignGateway does not guarantee transfer speed performance.
DesignGateway is exempted from any misoperation under user’s original environment.
[Inquiry]
URL :
http://www.design-gateway.com
Email :
info@design-gateway.com
Revision History
Revision
1.1E
1.2E
2.0E
Date
11-Jul-2012
23-Mar-2015
08-May-2017
Description
Initial English manual
Remove SATA description
Added AB07-USB3FMC-1.8VIF for 1.8V FMC environment
Copyright©2011 Design Gateway Co,.Ltd. All rights reserved.
Page 5/5