NXP Semiconductors
Technical Data
Document Number: MMDS36254H
Rev. 0, 01/2018
Advanced Doherty Alignment
Module (ADAM)
The MMDS36254H is an integrated module designed for use in base station
transmitters in conjunction with high power Doherty amplifiers. The device is
designed to enable accurate alignment of phase and amplitude on the carrier
and peaking amplifiers to ensure performance consistency, in particular for
asymmetric implementations. The MMDS36254H enables superior linearity--
efficiency trade--off while improving output power. It contains a 90 coupler,
digitally selectable phase shifters and step attenuators, and operates from a
single voltage supply. The MMDS36254H is suitable for transmit protocols such
as W--CDMA, UMTS and LTE using frequencies from 3400 to 3800 MHz, and is
controlled using a serial peripheral interface (SPI).
Features
Frequency: 3400–3800 MHz
Maximum RF Input Power: 25 dBm (CW)
Low Loss Power Splitter
0.25 dB Step Programmable Attenuators with 7.75 dB Maximum Range
6.5 per Bit Phase Shifters with 45.5 Maximum Range
Power up into a Selectable State
Single 5 Volt Supply
Supply Current: 10 mA
50 Ohm Operation (no external matching required)
TTL/CMOS/SPI Interface (1.8 V, 3.3 V Logic)
Cost--effective 32--pin, 6 mm QFN Surface Mount Plastic Package
MMDS36254HT1
3400–3800 MHz
ADAM – ADVANCED DOHERTY
ALIGNMENT MODULE
QFN 6
6
0
0 to –45.5
0 to 7.75 dB
0 to 7.75 dB
0 to –45.5
RF
out2
RF
in
–90
RF
out1
SERIAL DIGITAL INTERFACE
SDI
SCLK LCLK SDO
PUP
LEN
V
DD
BYP
GND
Figure 1. Functional Block Diagram
2018 NXP B.V.
MMDS36254HT1
1
RF Device Data
NXP Semiconductors
Table 1. Maximum Ratings
Rating
Supply Voltage
Logic Inputs (SCLK, LCLK, LEN, PUP, SDI)
RF Input Power (CW)
Storage Temperature Range
Junction Temperature
Symbol
V
DD
V
in
P
in
T
stg
T
J
Characteristic
Supply Voltage
DC Input Voltage (SCLK, LCLK, LEN, SDI)
Symbol
V
DD
V
in
Symbol
I
L
t
transition
P1dB
I
DD
|S32|
IRL
ORL
R
R
V
IL
V
IH
V
OH
V
OL
f
SCLK
Min
—
—
—
9.1
—
—
—
—
—
—
—
—
1.6
1.8
(1)
0
—
Min
4.5
0
Value
6
–0.5 to +3.63
25
–65 to +150
150
Unit
V
V
dBm
C
C
Table 2. Recommended Operating Conditions
Max
5.5
3.3
Unit
V
V
Table 3. Electrical Characteristics
(V
DD
= 5 Vdc, 3600 MHz, T
A
= 25C, 50 ohm system, in NXP Application Circuit)
Characteristic
Insertion Loss (Includes 3 dB power division and 2.5 dB loss)
Max Transition Time (Rising Edge of LCLK to RF
out
)
Power Input @ 1dB Compression
Supply Current
Isolation (S32)
Input Return Loss (S11)
Output Return Loss (S22, S33)
Phase Step
Phase Control Range
Attenuation Step
Attenuation Control Range
Max Input Voltage Logic Low
Min Input Voltage Logic High
SDO Output Voltage High
SDO Output Voltage Low
Clock Frequency (50% Duty Cycle)
1. Load = 20 pF @ maximum clock frequency.
Typ
6.5
350
39
9.7
35
15
15
6.5
45.5
0.25
7.75
—
—
—
—
—
Max
—
—
—
10.5
—
—
—
—
—
—
—
0.4
—
0.6
V
DD
0.4
26
Unit
dB
ns
dBm
mA
dB
dB
dB
/bit
dB/bit
dB
V
V
V
V
MHz
Table 4. Thermal Characteristics
Characteristics
Thermal Resistance, Junction to Case
Case Temperature 78.5C, P
out
= 0.01 W, Maximum Phase and
Attenuation State, P
in
= 25 dBm CW, 3600 MHz, V
DD
= 5 Vdc,
I
DD
= 11 mA
Symbol
R
JC
Value
(2)
10
Unit
C/W
Table 5. ESD Protection Characteristics
Test Methodology
Human Body Model (per JESD22--A114)
Charge Device Model (per JESD22--C101)
Class
1C
C2
Table 6. Moisture Sensitivity Level
Test Methodology
Per JESD22--A113, IPC/JEDEC J--STD--020
Rating
3
Package Peak Temperature
260
Unit
C
Table 7. Ordering Information
Device
MMDS36254HT1
Tape and Reel Information
T1 Suffix = 1,000 Units, 16 mm Tape Width, 7--inch Reel
QFN 6
6
Package
2. Refer to AN1955,
Thermal Measurement Methodology of RF Power Amplifiers.
Go to
http://www.nxp.com/RF
and search for AN1955.
MMDS36254HT1
2
RF Device Data
NXP Semiconductors
SDI LCLK V
DD
N.C. N.C. N.C. N.C. N.C.
32
SCLK
SDO
N.C.
RF
in
RF
in
N.C.
SDO
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RF
out2
RF
out2
BYP
PUP
LEN
GND
RF
out1
RF
out1
SDI LCLK V
DD
N.C. N.C. N.C. N.C. N.C.
(Top View)
Note: Exposed backside of the package is DC and RF ground.
Figure 2. Pin Connections
Table 8. Package Pin Description
Pin Number
1, 8
(1)
2
(2)
, 7
(1)
3, 6, 12, 13, 14, 15, 16,
25, 26, 27, 28, 29
4, 5
(3)
9, 32
(1)
10, 31
(1)
11, 30
(1)
17, 18
(3)
19
20
(4)
21
(5)
Pin Function
SCLK
SDO
N.C.
RF
in
SDI
LCLK
V
DD
RF
out1
GND
LEN
PUP
Serial Data Clock
Serial Data Output
No Connection
RF Input
Serial Data Input
Latch Clock
Supply Voltage (attenuators, phase shifters, SPI)
RF Output 1 (peaking amplifier path)
Ground
Logic Enable (active low)
Power--up Programming:
S
Minimum attenuation/minimum phase (0 dB/0)
S
Maximum attenuation/maximum phase (7.75 dB/–45.5)
22
(6)
23, 24
(3)
BYP
RF
out2
Internal Core Bypass Voltage (external 100 nF bypass capacitor)
RF Output 2 (carrier amplifier path)
Pin Description
1. Redundant pins are internally connected. User can connect to either of the internally connected paired pins:
1 and 8, 2 and 7, 9 and 32, 10 and 31, and 11 and 30.
2. The ADAM SPI interface can be connected to a common SPI bus, provided the SDO pin is not connected,
and treated as a write--only device.
3. Each RF pin pair should be tied together.
4. Logic low enables normal SPI operation. Logic high disables SPI and places device at 0 dB attenuation and
0
phase shift.
5. Logic low places device at 0 dB attenuation and 0 phase shift at power up. Logic high places device at 7.75 dB
attenuation and –45.5 phase shift. Because PUP pin has internal pull up, logic high can be set by no
connection to pin. Alternatively, it can be connected to BYP or a user--controlled V
in
.
6. Requires external capacitive decoupling to ground.
MMDS36254HT1
RF Device Data
NXP Semiconductors
3
Table 9. Serial Interface Timing Parameters
Symbol
t
SCLK
t
SCLKH
t
SCLKL
t
SU
t
H
t
OH
t
OV
(10 pF)
t
OV
(50 pF)
t
OV
(150 pF)
t
SETTLE
t
LCLKH
Serial Clock Period
Serial Clock Pulse Width High
Serial Clock Pulse Width Low
Serial Data Input Setup Time to SCLK Rising Edge
Serial Data Input Hold Time from SCLK Rising Edge
Serial Data Output Hold Time from SCLK Rising Edge
Serial Data Output Propagation Delay from SCLK Rising Edge
Serial Data Output Propagation Delay from SCLK Rising Edge
Serial Data Output Propagation Delay from SCLK Rising Edge
Serial Clock Rising Edge Setup Time to Latch Clock Rising Edge
Latch Clock Pulse Width High
Parameter
Min
38.5
10
10
—
—
1.6
—
—
—
—
10
Typ
—
—
—
—
—
—
5
15
35
—
—
Max
—
—
—
5
2
—
9
26
65
27
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
SCLK
t
SCLKH
SCLK
t
SU
t
H
t
SCLKL
SDI
t
OH
t
OV
SDO
t
SETTLE
t
LCLKH
LCLK
Figure 3. Serial Interface Timing Diagram
RF
out2
Attenuator
SCLK
SDI
LCLK
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
a
7
a
6
a
5
a
4
Phase
Attenuator
RF
out1
Phase
a
3
a
2
a
1
a
0
Figure 4. Serial Interface Bits Diagram
MMDS36254HT1
4
RF Device Data
NXP Semiconductors
Table 10. Logic Truth Table — RF
in
to RF
out1
a7
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
a6
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
a5
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
a4
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
a3
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Att.
(dB)
0
0.25
0.5
0.75
1.0
1.25
1.5
1.75
2.0
2.25
2.5
2.75
3.0
3.25
3.5
3.75
4.0
4.25
4.5
4.75
5.0
5.25
5.5
5.75
6.0
6.25
6.5
6.75
7.0
7.25
7.5
7.75
a2
L
L
L
L
H
H
H
H
a1
L
L
H
H
L
L
H
H
a0
L
H
L
H
L
H
L
H
Phase Shift
()
0
–6.5
–13
–19.5
–26
–32.5
–39
–45.5
Table 11. Logic Truth Table — RF
in
to RF
out2
b7
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
b6
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
b5
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
b4
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
b3
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Att.
(dB)
0
0.25
0.5
0.75
1.0
1.25
1.5
1.75
2.0
2.25
2.5
2.75
3.0
3.25
3.5
3.75
4.0
4.25
4.5
4.75
5.0
5.25
5.5
5.75
6.0
6.25
6.5
6.75
7.0
7.25
7.5
7.75
b2
L
L
L
L
H
H
H
H
b1
L
L
H
H
L
L
H
H
b0
L
H
L
H
L
H
L
H
Phase Shift
()
0
–6.5
–13
–19.5
–26
–32.5
–39
–45.5
Note:
ADAM contains a 32--bit shift register, with the last bit connected to the SDO signal. The SDO pin is intended for daisy--chaining
multiple ADAM devices rather than being used as an SPI bus connection; the SDO output is always actively driven, so it should not
be directly connected to the SPI bus.
MMDS36254HT1
RF Device Data
NXP Semiconductors
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
