74HC564
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
Rev. 03 — 11 November 2004
Product data sheet
1. General description
The 74HC564 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC564 is specified in compliance with JEDEC
standard no. 7A.
The 74HC564 is a octal D-type flip-flop featuring separate D-type inputs for each flip-flop
and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output
enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold
times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of
the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
flip-flops.
The 74HC564 is functionally identical to the 74HC574 but has inverting outputs. The
74HC564 is functionally identical to the 74HC534, but has a different pinning.
2. Features
s
s
s
s
s
s
s
3-state inverting outputs for bus oriented applications
8-bit positive-edge triggered register
Common 3-state output enable input
Independent register and 3-state buffer operation
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Multiple package options
s
Specified from
−40 °C
to +80
°C
and from
−40 °C
to +125
°C.
Philips Semiconductors
74HC564
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Symbol
t
PHL
, t
PLH
f
max
C
I
C
PD
Parameter
Conditions
Min
-
-
-
V
I
= GND to V
CC
[1]
Typ
15
127
3.5
27
Max
-
-
-
-
Unit
ns
MHz
pF
pF
propagation delay CP C
L
= 15 pF;
to Qn
V
CC
= 5 V
maximum clock
frequency
input capacitance
power dissipation
capacitance per
flip-flop
C
L
= 15 pF;
V
CC
= 5 V
-
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
4. Ordering information
Table 2:
Ordering information
Package
Temperature range
74HC564N
74HC564D
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP20
SO20
Description
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads;
body width 7.5 mm
Version
SOT146-1
SOT163-1
Type number
9397 750 13814
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 November 2004
2 of 18
Philips Semiconductors
74HC564
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
5. Functional diagram
2 D0
3 D1
4 D2
5 D3
6 D4
7 D5
8 D6
9 D7
FF1 TO
FF8
3 STATE
OUTPUTS
Q0 19
Q1 18
Q2 17
Q3 16
Q4 15
Q5 14
Q6 13
Q7 12
11 CP
1 OE
001aab936
Fig 1. Functional diagram
1
11
2
3
4
5
6
7
8
9
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
001aab934
EN
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
6
7
8
9
2
3
4
5
C1
19
18
17
16
15
14
13
12
001aab935
1D
Fig 2. Logic symbol
Fig 3. IEC logic symbol
9397 750 13814
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 November 2004
3 of 18
Philips Semiconductors
74HC564
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
FF
1
CP
Q
D
CP
FF
2
Q
D
CP
FF
3
Q
D
CP
FF
4
Q
D
CP
FF
5
Q
D
CP
FF
6
Q
D
CP
FF
7
Q
D
CP
FF
8
Q
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aab937
Fig 4. Logic diagram
6. Pinning information
6.1 Pinning
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
564
6
7
8
9
15 Q4
14 Q5
13 Q6
12 Q7
11 CP
001aab844
GND 10
Fig 5. Pin configuration
9397 750 13814
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 November 2004
4 of 18
Philips Semiconductors
74HC564
Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
6.2 Pin description
Table 3:
Symbol
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
CP
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Description
3-state output enable input (active LOW)
data input 0
data input 1
data input 2
data input 3
data input 4
data input 5
data input 6
data input 7
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
3-state flip-flop output 7
3-state flip-flop output 6
3-state flip-flop output 5
3-state flip-flop output 4
3-state flip-flop output 3
3-state flip-flop output 2
3-state flip-flop output 1
3-state flip-flop output 0
positive supply voltage
7. Functional description
7.1 Function table
Table 4:
Function table
[1]
Input
OE
Load and read
register
Load register and
disable output
[1]
Operating mode
CP
↑
↑
Dn
l
h
l
h
Internal
flip-flop
L
H
L
H
Output
Qn
H
L
Z
Z
L
H
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
↑
= LOW-to-HIGH clock transition.
9397 750 13814
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 11 November 2004
5 of 18
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