MCP47FEBXX
8-/10-/12-Bit Single/Dual Voltage Output Nonvolatile
Digital-to-Analog Converters with I
²
C™ Interface
Features
• Operating Voltage Range:
- 2.7V to 5.5V - Full Specifications
- 1.8V to 2.7V - Reduced Device Specifications
• Output Voltage Resolutions:
- 8-bit:
MCP47FEB0X
(256 Steps)
- 10-bit:
MCP47FEB1X
(1024 Steps)
- 12-bit:
MCP47FEB2X
(4096 Steps)
• Rail-to-Rail Output
• Fast Settling Time of 6 µs (typical)
• DAC Voltage Reference Source Options:
- Device V
DD
- External V
REF
pin (buffered or unbuffered)
- Internal Band Gap (1.22V typical)
• Output Gain Options:
- Unity (1x)
- 2x (when not using internal V
DD
as voltage
source)
• Nonvolatile Memory (EEPROM):
- User-programmed Power-on Reset
(POR)/Brown-out Reset (BOR) output setting
recall and device configuration bits
- Auto Recall of Saved DAC register setting
- Auto Recall of Saved Device Configuration
(Voltage Reference, Gain, Power-Down)
• Power-on/Brown-out Reset Protection
• Nonvolatile Memory Write Protect (WP) Bit
• Power-Down Modes:
- Disconnects output buffer (High Impedance)
- Selection of V
OUT
pull-down resistors
(100 k or 1 k)
• Low Power Consumption:
- Normal operation: <180 µA (Single), 380 µA
(Dual)
- Power-down operation: 650 nA typical
- EEPROM write cycle (1.9 mA maximum)
• I
2
C™ Interface:
- Slave address options: four predefined
addresses or user programmable (all 7 bits)
- Standard (100 kbps), Fast (400 kbps), and
High-Speed (up to 3.4 Mbps) modes
• Package Types: 8-lead TSSOP
• Extended Temperature Range: -40°C to +125°C
Package Types
MCP47FEBX1
TSSOP
Single
V
DD
1
V
REF0
2
V
OUT0
3
NC 4
8 SDA
7 SCL
6 LAT0/HVC
5 V
SS
MCP47FEBX2
TSSOP
Dual
V
DD
1
V
REF
(1)
2
V
OUT0
3
V
OUT1
4
Note 1:
8 SDA
7 SCL
6 LAT
(1)
/HVC
5 V
SS
This pin’s signal can be connected to DAC0
and/or DAC1.
General Description
The MCP47FEBXX are Single- and Dual-channel 8-bit,
10-bit, and 12-bit buffered voltage output Digital-to-
Analog Converters (DAC) with nonvolatile memory and
an I
2
C serial interface.
The V
REF
pin, the device V
DD
or the internal band gap
voltage can be selected as the DAC’s reference
voltage. When V
DD
is selected, V
DD
is connected
internally to the DAC reference circuit. When the V
REF
pin is used, the user can select the output buffer’s gain
to be 1 or 2. When the gain is 2, the V
REF
pin voltage
should be limited to a maximum of V
DD
/2.
These devices have a two-wire I
2
C-compatible serial
interface for Standard (100 kHz), Fast (400 kHz) or
High-Speed (1.7 MHz and 3.4 MHz) modes.
Applications
•
•
•
•
•
•
Set Point or Offset Trimming
Sensor Calibration
Low-Power Portable Instrumentation
PC Peripherals
Data Acquisition Systems
Motor Control
2015 Microchip Technology Inc.
DS20005375A-page 1
MCP47FEBXX
MCP47FEBX1 Device Block Diagram (Single-Channel Output)
V
DD
V
SS
SDA
SCL
Power-up/
Brown-out
Control
I
2
C™ Serial
Interface
Module and
Control Logic
(WiperLock™
Technology)
VREF1:VREF0
and PD1:PD0
Band Gap
(1.22V)
Memory (32x16)
DAC0 (Vol and NV)
VREF (Vol and NV)
Power-down (Vol and NV)
Gain (Vol and NV)
Status (Vol)
Slave Address (NV)
V
DD
PD1:PD0 and
VREF1:VREF0
+
-
(1)
V
DD
Resistor
Ladder
VREF1:VREF0
PD1:PD0
V
SS
Gain
Op
Amp
V
BG
V
REF0
V
OUT0
PD1:PD0
100 k
1 k
LAT0/HVC
Note 1:
If Internal Band Gap is selected, this buffer has a 2x gain. If the G bit = ‘1’, this is a total gain of 4.
DS20005375A-page 2
2015 Microchip Technology Inc.
MCP47FEBXX
MCP47FEBX2 Device Block Diagram (Dual-Channel Output)
V
DD
V
SS
SDA
SCL
Power-up/
Brown-out
Control
I
2
C™ Serial
Interface
Module and
Control Logic
(WiperLock™
Technology)
VREF1:VREF0
and PD1:PD0
Band Gap
V
BG
(1.22V)
Memory (32x16)
DAC0 and 1 (Vol & NV)
VREF (Vol and NV)
Power-down (Vol and NV)
Gain (Vol and NV)
Status (Vol)
Slave Addr (NV)
V
DD
PD1:PD0 and
VREF1:VREF0
+
(1)
-
PD1:PD0
V
SS
Resistor
Ladder
PD1:PD0
Gain
Op
Amp
V
OUT0
V
REF
VREF1:VREF0
LAT/HVC
VREF1:VREF0
and PD1:PD0 V
Band Gap
(1.22V)
Gain
DD
PD1:PD0 and
VREF1:VREF0
+(1)
-
PD1:PD0
V
SS
Resistor
Ladder
Op
Amp
100 k
1 k
V
DD
V
OUT1
intVR1
PD1:PD0
100 k
Specified
Operating Range
(V
DD
)
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
DS20005375A-page 3
VREF1:VREF0
Note 1:
If Internal Band Gap is selected, this buffer has a 2x gain, if the G bit = ‘1’, this is a total gain of 4.
Device Features
DAC Output
POR/BOR
Setting
(1)
Resolution
(bits)
# of
VREF
Inputs
1
1
1
1
1
1
Internal
band
gap
?
Yes
Yes
Yes
Yes
Yes
Yes
# of
Channels
Control
Interface
# of
LAT
Inputs
1
1
1
1
1
1
Device
Memory
MCP47FEB01
MCP47FEB11
MCP47FEB21
MCP47FEB02
MCP47FEB12
MCP47FEB22
Note 1:
1
1
1
2
2
2
8
10
12
8
10
12
I
2
C™
I
2
C
I
2
C
I C
I
2
C
2
7Fh
1FFh
7FFh
7Fh
1FFh
7FFh
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
EEPROM
I
2
C
The Factory Default value. The DAC output POR/BOR value can be modified via the nonvolatile DAC out-
put register(s).
2015 Microchip Technology Inc.
1 k
V
DD
MCP47FEBXX
NOTES:
DS20005375A-page 4
2015 Microchip Technology Inc.
MCP47FEBXX
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
Voltage on V
DD
with respect to V
SS
......................................................................................................... -0.6V to +6.5V
Voltage on all pins with respect to V
SS
............................................................................................... -0.6V to V
DD
+0.3V
Input clamp current, I
IK
(V
I
< 0, V
I
> V
DD
, V
I
> V
PP
on HV pins) .......................................................................... ±20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
DD
)...................................................................................................±20 mA
Maximum current out of V
SS
pin
Maximum current into V
DD
pin
(Single) ..........................................................................................................50 mA
(Dual)...........................................................................................................100 mA
(Single) ..........................................................................................................50 mA
(Dual)...........................................................................................................100 mA
Maximum current sourced by the V
OUT
pin ............................................................................................................20 mA
Maximum current sunk by the V
OUT
pin..................................................................................................................20 mA
Maximum current sunk by the V
REF
pin .................................................................................................................125 µA
Maximum input current source/sunk by SDA, SCL pins ..........................................................................................2 mA
Maximum output current sunk by SDA Output pin .................................................................................................25 mA
Total power dissipation
(1)
....................................................................................................................................400 mW
Package power dissipation (T
A
= +50°C, T
J
= +150°C)
TSSOP-8...................................................................................................................................................700 mW
ESD protection on all pins
±4
kV (HBM)
±400V
(MM)
±2
kV (CDM)
Latch-Up (per JEDEC JESD78A) @ +125°C ..................................................................................................... ±100 mA
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ...............................................................................................-55°C to +125°C
Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C
Maximum Junction Temperature (T
J
) .................................................................................................................... +150°C
† Notice:
Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Note 1:
Power dissipation is calculated as follows:
P
DIS
= V
DD
x {I
DD
-
I
OH
} +
{(V
DD
– V
OH
) x I
OH
} +
(V
OL
x I
OL
)
2015 Microchip Technology Inc.
DS20005375A-page 5
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
