MCP37220-200
MCP37D20-200
200 Msps, 14-Bit Low-Power Single-Channel ADC
Features
• Sample Rates: 200 Msps
• Signal-to-Noise Ratio (SNR) with f
IN
= 15 MHz
and -1 dBFS:
- 67.8 dBFS (typical) at 200 Msps
• Spurious-Free Dynamic Range (SFDR) with
f
IN
= 15 MHz and -1 dBFS:
- 96 dBc (typical) at 200 Msps
• Power Dissipation with LVDS Digital I/O:
- 346 mW at 200 Msps
• Power Dissipation with CMOS Digital I/O:
- 304 mW at 200 Msps, output clock = 100 MHz
• Power Dissipation Excluding Digital I/O:
- 256 mW at 200 Msps
• Power-Saving Modes:
- 89 mW during Standby
- 24 mW during Shutdown
• Supply Voltage:
- Digital Section: 1.2V, 1.8V
- Analog Section: 1.2V, 1.8V
• Selectable Full-Scale Input Range: up to 1.8 V
P-P
• Analog Input Bandwidth: 650 MHz
• Output Interface:
- Parallel CMOS, DDR LVDS
• Output Data Format:
- Two's complement or offset binary
• Optional Output Data Randomizer
• Digital Signal Post-Processing (DSPP) Options:
- Decimation filters for improved SNR
- Offset and Gain adjustment
- Digital Down-Conversion (DDC) with I/Q or
f
S
/8 output (MCP37D20-200)
• Built-In ADC Linearity Calibration Algorithms:
- Harmonic Distortion Correction (HDC)
- DAC Noise Cancellation (DNC)
- Dynamic Element Matching (DEM)
- Flash Error Calibration
• Serial Peripheral Interface (SPI)
• Package Options:
- VTLA-124 (9 mm x 9 mm x 0.9 mm)
- TFBGA-121 (8 mm x 8 mm)
• No external reference decoupling capacitor
required for TFBGA Package
• Industrial Temperature Range: -40°C to +85°C
Typical Applications
•
•
•
•
•
•
Communication Instruments
Microwave Digital Radio
Cellular Base Stations
Radar
Scanners and Low-Power Portable Instruments
Industrial and Consumer Data Acquisition System
Device Offering
(1)
Part Number
MCP37220-200
MCP37D20-200
MCP37210-200
MCP37D10-200
1:
Sample Rate
200 Msps
200 Msps
200 Msps
200 Msps
Resolution
14
14
12
12
Digital Decimation
(FIR Filters)
Yes
Yes
Yes
Yes
Digital
Down-Conversion
No
Yes
No
Yes
Noise-Shaping
Requantizer
No
No
Yes
Yes
Devices in the same package type are pin-compatible.
2015-2016 Microchip Technology Inc.
DS20005396B-page 1
MCP37220-200 AND MCP37D20-200
Functional Block Diagram
AV
DD12
AV
DD18
GND
DV
DD12
DV
DD18
CLK+
CLK-
Clock
Selection
Duty Cycle
Correction
DLL
PLL
Output Clock Control
A
IN
+
Pipelined
ADC
A
IN
-
V
REF+
V
CM
SENSE
Reference
Generator
Internal Registers
V
BG
V
REF-
Output Control:
- CMOS
- DDR LVDS
DCLK+
DCLK-
Digital Signal Post-Processing:
- Decimation
- Offset/Gain Adjustment
MCP37D20-200:
- Digital Down-Conversion
OVR
WCK
Q[13:0]
REF+
REF-
SDIO
SCLK
CS
DS20005396B-page 2
2015-2016 Microchip Technology Inc.
MCP37220-200 AND MCP37D20-200
Description
The MCP37220-200 is a single-channel 200 Msps
14-bit pipelined ADC, with built-in high-order digital
decimation filters, gain and offset adjustment.
The MCP37D20-200 is also a single-channel 200 Msps
14-bit
pipelined
ADC,
with
built-in
digital
down-conversion in addition to the features offered by
the MCP37220-200.
Both devices feature harmonic distortion correction
and DAC noise cancellation that enables high-
performance specifications with SNR of 67.8 dBFS
(typical) and SFDR of 96 dBc (typical).
The output decimation filter option improves SNR
performance up to 83.9 dBFS with the 512x decimation
setting.
The digital down-conversion option in the MCP37D20-200
can be utilized with the decimation and quadrature output
(I and Q data) options and offers great flexibility in digital
communication system design, including cellular
base-stations and narrow-band communication systems.
These A/D converters exhibit industry-leading
low-power performance with only 348 mW operation
while using the LVDS output interface at 200 Msps.
This superior low-power operation, coupled with high
dynamic performance, makes these devices ideal for
portable communication devices, sonar, radar and
high-speed data acquisition systems.
These devices also include various features designed
to maximize flexibility in the user’s applications and
minimize system cost, such as a programmable PLL
clock, output data rate control and phase alignment,
and programmable digital pattern generation. The
device’s operational modes and feature sets are
configured by setting up the user-programmable
internal registers.
The device samples the analog input on the rising edge
of the clock. The digital output code is available after
23 clock cycles of data latency. Latency will increase if
any of the digital signal post-processing (DSPP)
options are enabled.
The differential full-scale analog input range is
programmable up to 1.8 V
P-P
. The ADC output data
can be coded in two's complement or offset binary
representation, with or without the data randomizer
option. The output data is available with a full-rate
CMOS or Double-Data-Rate (DDR) LVDS interface.
The device is available in Pb-free VTLA-124 and
TFBGA-121 packages. The device operates over the
commercial temperature range of -40°C to +85°C.
Dimension:
9 mm x 9 mm x 0.9 mm
Package Types
Bottom View
(a) VTLA-124 Package.
Bottom View
Dimension:
8 mm x 8 mm x 1.08 mm
Ball Pitch:
0.65 mm
Ball Diameter:
0.4 mm
(b) TFBGA-121 Package.
2015-2016 Microchip Technology Inc.
DS20005396B-page 3
MCP37220-200 AND MCP37D20-200
NOTES:
DS20005396B-page 4
2015-2016 Microchip Technology Inc.
MCP37220-200 AND MCP37D20-200
1.0
PACKAGE PIN CONFIGURATIONS
AND FUNCTION DESCRIPTIONS
Top View
(Not to Scale)
NC
A68
A1
A2
B1
A3
B2
A4
NC
A5
B4
A6
B5
A7
B6
A8
B7
A9
B8
NC
A10
B9
A11
B10
A12
B11
A13
B12
A14
B13
A15
A16
A17
NC
B14
A18
AV
DD12
B15
A19
Note 2
B16
CLK-
B17
A21
Note 1
ADR0 SYNC GND
RESET DCLK+
B18
B19
A23
B20
B21
A25
B22
B23
A27
DCLK-
DV
DD18
AV
DD18
A
IN
-
AV
DD12
A66
B55
A65
B54
A
IN
+
A64
B53
A63
B52
AV
DD18
A62
NC
A61
AV
DD12
V
BG
A60
B49
A59
REF-
A58
REF+
AV
DD12
V
CM
A57
A56
B46
REF+
B45
A55
SCLK SDIO
A54
A53
A52
NC
A51
A50
Note 2
A49
B41
A48
B40
A47
B39
A46
A45
WCK/OVR-
(WCK)
A44 Q12/Q6-
A43 Q11/Q5+
A67
B56
B51
B50
B48
B47
B44
CS
B43
DV
DD18
B42
Note 2
AV
DD18
Note 2
SENSE REF-
B3
VTLA-124
(9 mm x 9 mm x 0.9 mm)
DV
DD12
WCK/OVR+
(OVR) B38
Q13/Q6+ B37
Note 2
EP
(GND)
Note 4
DV
DD18
B36
Q10/Q5- B35
A42 Q9/Q4+
Q8/Q4- B34
Q7/Q3+ B33
Q5/Q2+ B32
A39 Q4/Q2-
DV
DD18
B31
A38 Q3/Q1+
Q2/Q1- B30
A37
B29
A36
Q0/Q0-
DV
DD18
B25
A29
B26
B27
A31
B28
A33
NC
A35
A34
Note 2
B24
A41
DV
DD18
A40 Q6/Q3-
AV
DD12
A20
A22
A24
A26
A28
A30
A32
CLK+
AV
DD18
SLAVE
DV
DD12
CAL
TP
Note 3
DV
DD12
Q1/Q0+
Note 1:
Tie to GND or DV
DD18
. ADR1 is internally bonded to GND.
2:
NC – Not connected pin. This pin can float or be tied to ground.
3:
TP – Test pin. Leave this pin floating and do not tie to ground or supply.
4:
Exposed pad (EP – back pad of the package) is the common ground (GND) for analog and digital
supplies. Connect this pad to a clean ground reference on the PCB.
FIGURE 1-1:
VTLA-124 Package.
2015-2016 Microchip Technology Inc.
DS20005396B-page 5
嵌入式系统
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