DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD72852
IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI
The
µ
PD72852 is a two-port physical layer LSI that complies with the IEEE1394a-2000 specifications.
The
µ
PD72852 supports transfers of up to 400 Mbps and consumes less power than the
µ
PD72850B. The
µ
PD72852 is suitable for battery systems with an IEEE1394 interface.
FEATURES
• The two-port physical layer LSI complies with IEEE1394a-2000
• Fully interoperable with IEEE1394 std 1394 Link (FireWire
TM
, i.LINK
TM
)
• Meets Intel
TM
Mobile Power Guideline 2000
• Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-
speed concatenation, arbitration acceleration, fly-by concatenation
• Fully compliant with OHCI requirements
• Small package: 64-pin plastic LQFP
• Super low power: 68 mA (Operating mode)
: 115
µ
A (Suspend mode)
• Data rate: 400/200/100 Mbps
• Supports PHY pinging and remote PHY access packets
• 3.3 V single power supply (if power not supplied via node: 3.0 V single power supply)
• 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency
• 64-bit flexible register incorporated in PHY register
• Electrically isolated Link interface
• Supports LPS/Link-on as part of PHY/Link interface
• External filter capacitors for PLL not required
• Extended Resume signaling for compatibility with legacy DV devices
• System power management by signaling of node power class information
• Cable power monitor (CPS) is equipped
ORDERING INFORMATION
Part number
Package
64-pin plastic LQFP (10 x 10)
µ
PD72852GB-8EU
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14920EJ3V0DS00 (3rd edition)
Date Published March 2001 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2000
µ
PD72852
PIN NAME
AGND
AV
DD
CMC
CPS
CTL0
CTL1
D0-D7
DGND
DIRECT
DV
DD
IC(AL)
IC(DL)
LKON
LPS
LREQ
PC0-PC2
RESETB
RI1
SCLK
SPD
SUS/RES
TEST
TpA0n
TpA0p
TpA1n
TpA1p
TpB0n
TpB0p
TpB1n
TpB1p
TpBias0
TpBias1
XI
XO
: Analog GND
: Analog Power
: Configuration Manager Capable
: Cable Power Status
: Link Interface Control (bit 0)
: Link Interface Control (bit 1)
: Data Input/Output
: Digital GND
: PHY/Link Isolation Barrier Control Input
: Digital V
DD
: Internally Connected (Low Clamped)
: Internally Connected (Low Clamped)
: Link-on Signal Output
: Link Power Status Input
: Link Request Input
: Power Class Set Input
: Power-on Reset Input
: Reference Power Set, Connect Resistor 1
: Link Control Output Clock
: Speed Select
: Suspend/Resume Function Select
: Test Pin (Low Clamped)
: Port 0 Twisted Pair Cable A Negative Phase I/O
: Port 0 Twisted Pair Cable A Positive Phase I/O
: Port 1 Twisted Pair Cable A Negative Phase I/O
: Port 1 Twisted Pair Cable A Positive Phase I/O
: Port 0 Twisted Pair Cable B Negative Phase I/O
: Port 0 Twisted Pair Cable B Positive Phase I/O
: Port 1 Twisted Pair Cable B Negative Phase I/O
: Port 1 Twisted Pair Cable B Positive Phase I/O
: Port 0 Twisted Pair Output
: Port 1 Twisted Pair Output
: Crystal Oscillator Connection XI
: Crystal Oscillator Connection XO
4
Data Sheet S14920EJ3V0DS
µ
PD72852
CONTENTS
1. PIN
1.1
1.2
1.3
1.4
1.5
1.6
FUNCTIONS..................................................................................................................................... 7
Cable Interface Pins ........................................................................................................................ 7
Link Interface Pins........................................................................................................................... 7
Control Pins ..................................................................................................................................... 8
IC ....................................................................................................................................................... 8
Power Supply Pins .......................................................................................................................... 8
Other Pins ........................................................................................................................................ 8
2. PHY REGISTERS..................................................................................................................................... 9
2.1 Complete Structure for PHY Registers.......................................................................................... 9
2.2 Port Status Page (Page 000)......................................................................................................... 12
2.3 Vendor ID Page (Page 001) ........................................................................................................... 13
2.4 Vendor Dependent Page (Page 111 : Port_select 0001) ............................................................ 13
3. INTERNAL FUNCTION.......................................................................................................................... 14
3.1 Link Interface ................................................................................................................................. 14
3.1.1 Connection Method............................................................................................................................... 14
3.1.2 LPS (Link Power Status)....................................................................................................................... 14
3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins .................................................................................................... 14
3.1.4 SCLK..................................................................................................................................................... 14
3.1.5 LKON .................................................................................................................................................... 15
3.1.6 DIRECT................................................................................................................................................. 15
3.1.7 Isolation Barrier..................................................................................................................................... 15
3.2 Cable Interface............................................................................................................................... 17
3.2.1 Connections .......................................................................................................................................... 17
3.2.2 Cable Interface Circuit .......................................................................................................................... 18
3.2.3 Unused Ports ........................................................................................................................................ 18
3.2.4 CPS....................................................................................................................................................... 18
3.3 Suspend/Resume .......................................................................................................................... 18
3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)...................................................................................... 18
3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”) ...................................................................................... 18
3.4 PLL and Crystal Oscillation Circuit ............................................................................................. 19
3.4.1 Crystal Oscillation Circuit ...................................................................................................................... 19
3.4.2 PLL........................................................................................................................................................ 19
3.5
3.6
3.7
3.8
CMC ................................................................................................................................................ 19
PC0-PC2 ......................................................................................................................................... 19
RESETB .......................................................................................................................................... 19
RI1 ................................................................................................................................................... 19
4. PHY/LINK INTERFACE ......................................................................................................................... 20
4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface ............................................ 20
4.2 Link-on Indication.......................................................................................................................... 21
4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7)....................................................... 22
4.3.1 CTL0, CTL1 .......................................................................................................................................... 22
4.3.2 LREQ .................................................................................................................................................... 22
4.3.3 SCLK Timing......................................................................................................................................... 26
Data Sheet S14920EJ3V0DS
5