LT1381
Low Power 5V RS232 Dual
Driver/Receiver with
0.1µF Capacitors
FEATURES
s
s
s
s
s
s
s
s
s
DESCRIPTIO
s
s
ESD Protection over
±10kV
Low Cost
Uses Small Capacitors: 0.1µF
CMOS Comparable Low Power: 40mW
Operates from a Single 5V Supply
120kBaud Operation for R
L
= 3k, C
L
= 2500pF
250kBaud Operation for R
L
= 3k, C
L
= 1000pF
Rugged Bipolar Design
Outputs Assume a High Impedance State When
Powered Down
Absolutely No Latchup
Available in Narrow SO Package
APPLICATI
s
s
s
s
s
S
The LT
®
1381 is a dual RS232 driver/receiver pair with
integral charge pump to generate RS232 voltage levels
from a single 5V supply. The circuit features rugged
bipolar design to provide operating fault tolerance and
ESD protection unmatched by competing CMOS designs.
Using only 0.1µF external capacitors, the circuit con-
sumes only 40mW of power and can operate to 120kbaud
even while driving heavy capacitive loads. New ESD struc-
tures on the chip allow the LT1381 to survive multiple
±10kV
strikes, eliminating the need for costly TransZorbs
®
on the RS232 line pins. Driver outputs are protected from
overload and can be shorted to ground or up to
±25V
without damage. During power-off conditions, driver and
receiver outputs are in a high impedance state, allowing
line sharing.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TransZorb
®
is a registered trademark of General Instruments, GSI
Portable Computers
Battery-Powered Systems
Power Supply Generator
Terminals
Modems
TYPICAL APPLICATI
+
0.1µF
1
3
LT1381
16
2
5V INPUT
+
0.1µF
6
0.1µF
14
V
+
OUT
DRIVER
OUTPUT
R
L
= 3k
C
L
= 2500pF
+
0.1µF
4
5
11
V
–
OUT
RS232 OUTPUT
LOGIC
INPUTS
10
12
7
13
5k
RECEIVER
R
OUTPUT
C
L
= 50pF
RS232 OUTPUT
RS232 INPUT
INPUT
LOGIC
OUTPUTS
9
S
8
5k
15
RS232 INPUT
LT1381 • TA01
U
Output Waveforms
LT1381 • TA02
UO
+
UO
1
LT1381
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
C1
+
V
+
C1
–
C2
+
C2
–
V
–
TR2 OUT
REC2 IN
1
2
3
4
5
6
7
8
16 V
CC
15 GND
14 TR1 OUT
13 REC1 IN
12 REC1 OUT
11 TR1 IN
10 TR2 IN
9
REC2 OUT
Supply Voltage (V
CC
) ................................................ 6V
V
+
........................................................................ 13.2V
V
–
...................................................................... –13.2V
Input Voltage
Driver ........................................................... V
–
to V
+
Receiver ............................................... – 30V to 30V
Output Voltage
Driver ................................. (V
+
– 30V) to (V
–
+ 30V)
Receiver ................................. – 0.3V to (V
CC
+ 0.3V)
Short-Circuit Duration
V
+
................................................................... 30 sec
V
–
................................................................... 30 sec
Driver Output .............................................. Indefinite
Receiver Output .......................................... Indefinite
Operating Temperature Range
LT1381C ................................................. 0°C to 70°C
LT1381I .............................................. – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
LT1381CN
LT1381CS
LT1381IS
S PACKAGE
N PACKAGE
16-LEAD PLASTIC DIP 16-LEAD PLASTIC SOIC
T
JMAX
= 125°C,
θ
JA
= 90°C/ W,
θ
JC
= 46°C/W (N)
T
JMAX
= 125°C,
θ
JA
= 110°C/ W,
θ
JC
= 34°C/W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
PARAMETER
Power Supply Generator
V
+
Output
V
–
Output
Supply Current (V
CC
)
Supply Rise Time
Oscillator Frequency
Driver
Output Voltage Swing
Logic Input Voltage Level
Logic Input Current
Output Short-Circuit Current
Output Leakage Current
Data Rate
Slew Rate
Propagation Delay
CONDITIONS
(Note 2)
MIN
TYP
7.9
– 7.0
8
q
MAX
UNITS
V
V
mA
mA
ms
kHz
V
V
V
V
µA
mA
µA
kBaud
kBaud
(Note 3), T
A
= 25°C
C1 = C2 = C3 = C4 = 0.1µF
14
16
0.2
130
Positive
Negative
q
q
q
q
q
Load = 3k to GND
Input Low Level (V
OUT
= High)
Input High Level (V
OUT
= Low)
0.8V
≤
V
IN
≤
2.0V
V
OUT
= 0V
Power Off V
OUT
=
±15V
R
L
= 3k, C
L
= 2500pF
R
L
= 3k, C
L
= 1000pF
R
L
= 3k, C
L
= 51pF
R
L
= 3k, C
L
= 2500pF
Output Transition t
HL
High to Low (Note 4)
Output Transition t
LH
Low to High
5.0
2.0
9
7.5
– 6.3
1.4
1.4
5
17
10
– 5.0
0.8
20
100
q
120
250
4
15
6
0.6
0.5
30
1.3
1.3
2
U
V/µs
V/µs
µs
µs
W
U
U
W W
W
LT1381
ELECTRICAL CHARACTERISTICS
PARAMETER
Receiver
Input Voltage Thresholds
Hysteresis
Input Resistance
Output Voltage
Output Short-Circuit Current
Propagation Delay
(Note 6)
CONDITIONS
(Note 2)
MIN
0.8
q
TYP
1.3
1.7
0.4
5
0.2
4.2
– 20
20
250
350
MAX
UNITS
V
V
V
kΩ
V
V
mA
mA
ns
ns
Input Low Threshold (V
OUT
= High)
Input High Threshold (V
OUT
= Low)
2.4
1.0
7
0.4
– 10
600
600
0.1
3
Output Low, I
OUT
= – 1.6mA
Output High, I
OUT
= 160µA (V
CC
= 5V)
Sinking Current, V
OUT
= V
CC
Sourcing Current, V
OUT
= 0V
Output Transition t
HL
High-to-Low (Note 5)
Output Transition t
LH
Low-to-High
q
q
3.5
10
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2:
Testing done at V
CC
= 5V, unless otherwise specified.
Note 3:
Supply current is measured as the average over several charge
pump cycles. C
+
= C
–
= C1 = C2 = 0.1µF. All outputs are open, with all
driver inputs tied high.
Note 4:
For driver delay measurements, R
L
= 3k and C
L
= 51pF. Trigger
points are set between the driver’s input logic threshold and the output
transition to the zero crossing (t
HL
= 1.4V to 0V and t
LH
= 1.4V to 0V).
Note 5:
For receiver delay measurements, C
L
= 51pF. Trigger points are
set between the receiver’s input logic threshold and the output transition
to standard TTL/CMOS logic threshold (t
HL
= 1.3V to 2.4V and t
LH
= 1.7V
to 0.8V).
Note 6:
Tested at V
IN
=
±10V.
TYPICAL PERFOR A CE CHARACTERISTICS
Driver Maximum Output Voltage
vs Load Capacitance
9.0
2 DRIVERS LOADED
8.5
8.0
7.5
20k BAUD
7.0
6.5
6.0
5.5
120k BAUD
5.0
0
1
2
3 4 5 6 7 8
LOAD CAPACITANCE (nF)
9
10
60k BAUD
DRIVER OUTPUT VOLTAGE (V)
PEAK OUTPUT VOLTAGE (V)
PEAK OUTPUT VOLTAGE (V)
U W
LT1381 • TPC01
Driver Minimum Output Voltage
vs Load Capacitance
–4.0
2 DRIVERS LOADED
–4.5
–5.0
60k BAUD
–5.5
–6.0
–6.5
–7.0
0
1
2
3 4 5 6 7 8
LOAD CAPACITANCE (nF)
9
10
120k BAUD
10
8
6
4
2
0
–2
–4
–6
–8
Driver Output Voltage
R
L
= 3k
V
CC
= 5.5V
V
CC
= 5V
V
CC
= 4.5V
OUTPUT HIGH
OUTPUT LOW
V
CC
= 4.5V
V
CC
= 5V
V
CC
= 5.5V
20k BAUD
–10
–55 –25
50
25
0
75
TEMPERATURE (°C)
100
125
LT1381 • TPC02
LT1381 • TPC03
3
LT1381
TYPICAL PERFOR A CE CHARACTERISTICS
Receiver Input Threshold
3.00
2.75
THRESHOLD VOLTAGE (V)
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
–55 –25
50
25
0
75
TEMPERATURE (°C)
100
125
0
0
25
50
75
100
DATA RATE (kBaud)
125
150
0.1
–55 –25
50
25
0
75
TEMPERATURE (°C)
100
125
LEAKAGE CURRENT (µA)
SUPPLY CURRENT (mA)
INPUT HIGH
INPUT LOW
Receiver Short-Circuit Current
50
ISC
–
SHORT-CIRCUIT CURRENT (mA)
SHORT-CIRCUIT CURRENT (mA)
40
20
15
10
5
0
–55 –25
30
ISC
+
20
SLEW RATE (V/µs)
10
0
–55 –25
50
25
0
75
TEMPERATURE (°C)
LTLT1381 • TPC07
V
+
Compliance Curve
10
V
+
(1µF)
8
V
+
(0.1µF)
–8
–10
V
+
(V)
V
–
(V)
6
4
2
0
0
5
10
+
(mA)
LOAD CURRENT
4
U W
LT1381 • TPC04
Supply Current vs Data Rate
50
2 DRIVERS ACTIVE
R
L
= 3k
C
L
= 2500pF
100
Driver Leakage in Shutdown
40
10
30
20
1
V
OUT
= 30V
V
OUT
= –30V
10
LT1381 • TPC05
LT1381 • TPC06
Driver Short-Circuit Current
30
25
ISC
+
20
18
16
14
12
10
8
6
4
2
Slew Rate vs Load Capacitance
ISC
–
+SLEW RATE
–SLEW RATE
100
125
50
25
75
0
TEMPERATURE (˚C)
100
125
0
0
1
3
2
CAPACITANCE (nF)
4
5
LT1381 • TPC08
LT1381 • TPC09
V
–
Compliance Curve
V
–
(1µF)
–6
V
–
(0.1µF)
–4
–2
15
LT1381 • TPC10
0
0
5
10
–
(mA)
LOAD CURRENT
15
LT1381 • TPC11
LT1381
PI FU CTIO S
C1
+
, C1
–
, C2
+
, C2
–
(Pins 1, 3, 4, 5):
Commutating
Capacitor Inputs. These pins require two external capaci-
tors C
≥
0.1µF: one from C1
+
to C1
–
and another from C2
+
to C2
–
. C1 may be deleted if a separate 12V supply is
available and connected to pin C1
+
.
V
+
(Pin 2):
Positive Supply Output (RS232 Drivers).
V
+
≈
2V
CC
– 2.1V. This pin requires an external charge
storage capacitor C
≥
0.1µF, tied to ground or V
CC
. Larger
value capacitors may be used to reduce supply ripple. With
multiple transceivers, the V
+
and V
–
pins may be paralleled
into common capacitors.
V
–
(Pin 6):
Negative Supply Output (RS232 Drivers).
V
–
≈
–(2V
CC
– 3V). This pin requires an external charge
storage capacitor C
≥
0.1µF. Larger value capacitors may
be used to reduce supply ripple. With multiple transceiv-
ers, the V
+
and V
–
pins may be paralleled into common
capacitors.
TR2 OUT, TR1 OUT (Pin 7, 14):
Driver Outputs at RS232
Voltage Levels. Driver output swing meets RS232 levels
for loads up to 3k. Slew rates are controlled for lightly
loaded lines. Output current capability is sufficient for
load conditions up to 2500pF. Outputs are in a high
impedance state when V
CC
= 0V. Outputs are fully short-
circuit protected from V
–
+ 25V to V
+
– 25V. Applying
higher voltages will not damage the device if the over-
drive is moderately current limited. Short circuits on one
output can load the power supply generator and may
disrupt the signal levels of the other outputs. The driver
outputs are protected against ESD to
±10kV
for human
body model discharges.
REC2 IN, REC1 IN (Pins 8, 13):
Receiver Inputs. These
pins accept RS232 level signals (±30V) into a protected 5k
terminating resistor. The receiver inputs are protected
against ESD to
±10kV
for human body model discharges.
Each receiver provides 0.4V of hysteresis for noise immu-
nity. Open receiver inputs assume a logic low state.
REC2 OUT, REC1 OUT (Pins 9, 12):
Receiver Outputs with
TTL/CMOS Voltage Levels. Outputs are fully short-circuit
protected to ground or V
CC
with the power ON or OFF.
TR2 IN, TR1 IN (Pins 10, 11):
RS232 Driver Input Pins.
These inputs are TTL/CMOS compatible. Inputs should
not be allowed to float. Tie unused inputs to V
CC
.
GND (Pin 15):
Ground Pin.
V
CC
(Pin 16):
5V Input Supply Pin. This pin should be
decoupled with a 0.1µF ceramic capacitor close to the
package pin. Insufficient supply bypassing can result in
low output drive levels and erratic charge pump operation.
ESD PROTECTIO
The RS232 line inputs of the LT1381 have on-chip protec-
tion from ESD transients up to
±10kV.
The protection
structures act to divert the static discharge safely to
system ground. In order for the ESD protection to function
effectively, the power supply and ground pins of the circuit
must be connected to ground through low impedances.
The power supply decoupling capacitors and charge pump
storage capacitors provide this low impedance in normal
application of the circuit. The only constraint is that low
ESR capacitors must be used for bypassing and charge
storage. ESD testing must be done with pins V
CC
, V
+
, V
–
and GND shorted to ground or connected with low ESR
capacitors.
U
U
U
U
ESD Test Circuit
1
C1
+
V
+
C1
–
C2
+
C2
–
V
–
LT1381
5V V
CC
GND
16
+
0.1µF
0.1µF
+
2
3
+
15
0.1µF
RS232
LINE PINS
PROTECTED
TO
±10kV
TR1 OUT 14
REC1 IN 13
REC1 OUT 12
TR1 IN 11
TR2 IN 10
REC2 OUT 9
+
0.1µF
0.1µF
4
5
+
6
RS232
LINE PINS
PROTECTED
TO
±10kV
7 TR2 OUT
8 REC2 IN
LT1381 • ESD TC
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
