The MAX77813 is a high-efficiency buck-boost converter
targeted for single-cell Li-ion battery powered applications.
The device supports an input voltage range from 2.30V to
5.5V with an output voltage range from 2.60V to 5.14V.
The device can support up to 2A and 3A of output current
in boost and buck modes respectively. The peak efficiency
of 97% allows longer operating time.
The device is designed to support seamless transitions
between buck and boost modes. A unique control algorithm
allows high-efficiency and outstanding performances
in line/load transient responses. The I
2
C-compatible
serial interface provides design flexibility to optimize
performance along with protection features. The output
voltage can be dynamically adjusted for finer control of
system power consumption. The device supports two
input current limits selected by ILIM logic input.
The MAX77813 is available in a 1.827mm x 2.127mm,
20-bump wafer-level package (WLP).
Features and Benefits
●
V
IN
Range: 2.30V to 5.5V
●
V
OUT
Range: 2.60V to 5.14V
(I
2
C Programmable in 20mV Step)
●
Up to 2A Output Current in Boost Mode
(V
IN
= 3.0V, V
OUT
= 3.4V, ILIM = High)
●
Up to 3A Output Current in Buck Mode (ILIM = High)
●
Up to 97% Peak Efficiency
●
SKIP Mode for Optimal Light Load Efficiency
●
55µA (Typ) Low Quiescent Current
●
3.4MHz High Speed I
2
C Serial Interface
●
Input Current Limit Selection Pin
●
Power-OK Output
●
2.5MHz Switching Frequency
●
Protection Features
• Soft-Start
• Thermal Shutdown
• Overvoltage Protection
• Short Circuit Protection
●
1.827mm x 2.127mm, 20-Bump WLP
Ordering Information
appears at end of data sheet.
Applications
●
Single-Cell Li-ion Powered Applications
●
Handheld Scanners, Mobile Payment Terminals,
Security Cameras
●
AR/VR Headsets
Typical Application Circuit
1µH
LXBB1
V
IN
10µF
V
IO
0.1µF
1.5kΩ
POK
SDA
SCL
1.5kΩ
100kΩ
POK
SDA
SCL
INBB
V
SYS
1µF
V
IO
LXBB2
OUTBB
FB_BB
PGNDBB
47µF
V
OUT
MAX77813
EN
ILIM
GND
EN
ILIM
19-8238; Rev 0; 10/18
MAX77813
High-Efficiency Buck-Boost Converter
Absolute Maximum Ratings
SYS, V
IO
to GND .................................................-0.3V to +6.0V
INBB, OUTBB to PGNDBB ..................................-0.3V to +6.0V
PGNDBB to GND .................................................-0.3V to +0.3V
SCL, SDA to GND ................................... -0.3V to (V
VIO
+ 0.3V)
EN, ILIM, POK to GND........................... -0.3V to (V
SYS
+ 0.3V)
FB_BB to GND ...................................-0.3V to (V
OUTBB
+ 0.3V)
LXBB1 to PGNDBB ............................... -0.3V to (V
INBB
+ 0.3V)
LXBB2 to PGNDBB ............................-0.3V to (V
OUTBB
+ 0.3V)
LXBB1/LXBB2 Continuous RMS Current (Note 1) ..............3.2A
Operating Junction Temperature Range .......... -40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Soldering Temperature (Reflow)......................................+260°C
Note 1:
LXBB1/LXBB2 node has internal clamp diodes to PGNDBB and INBB. Applications that give forward bias to these diodes
should ensure that the total power loss does not exceed the power dissipation limit of the IC package.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
WLP
Package Code
Outline Number
Land Pattern Number
Thermal Resistance, Four-Layer Board:
Junction to Ambient Thermal Resistance (θ
JA
)
55.49°C/W
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages.
Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
W201F2+1
21-0771
Refer to
Application Note 1891
www.maximintegrated.com
Maxim Integrated
│
2
MAX77813
High-Efficiency Buck-Boost Converter
Buck-Boost Electrical Characteristics
(V
SYS
= V
INBB
= +3.8V, V
FB_BB
= V
OUTBB
= +3.3V, T
J
= -40°C to +125°C, typical values are at T
A
≈ T
J
= +25°C, unless otherwise
noted.) (Note 4)
PARAMETER
GENERAL
Input Voltage Range
Shutdown Supply Current
V
INBB
I
SHDN_25C
I
SHDN_125C
I
Q_SKIP
I
Q_PWM
Active Discharge Resistance
Thermal Shutdown Threshold
H-BRIDGE
Output Voltage Range
V
OUT
V
OUT_ACC1
V
OUT_ACC2
Line Regulation
Load Regulation
Line Transient Response
V
OS1
V
US1
V
OS2
V
US2
I
2
C programmable (20mV Step)
FPWM mode, VOUT[6:0] = 0x28, no load,
T
J
= +25°C
SKIP mode, VOUT[6:0] = 0x28,
no load, T
J
= +25°C
V
INBB
= 2.63V to 5.5V
(Note 5)
I
OUT
= 1.0A, V
INBB
changes from 3.4V to
2.9V in 25µs (20mV/µs),
L = 1µH, C
OUT_NOM
= 47µF (Note 5)
V
INBB
= 3.4V,
I
OUT
changes from 10mA to 1.5A in 15µs,
L = 1µH, C
OUT_NOM
= 47µF (Note 5)
BB_RU_SR = 0
BB_RU_SR = 1
BB_RD_SR = 0
BB_RD_SR = 1
η
TYP
η
PK
I
LIM_LXBB
R
DSON(PMOS)
R
DSON(NMOS)
f
SW
I
OUT
= 100mA (Note 5)
(Note 5)
ILIM = high
LXBB1/2 Current Limit
High-Side PMOS ON
Resistance
Low-Side NMOS ON
Resistance
Switching Frequency
ILIM = low
(OTP: 1.8A, 2.2A, 2.7A, 3.1A)
I
LXBB
= 100mA per switch
I
LXBB
= 100mA per switch
PWM mode, T
J
= +25°C
2.25
3.70
1.2
2.60
-1.0
-1.0
0.200
0.125
50
5.14
+1.0
%
+4.5
%/V
%/A
mV
V
R
DISCHG
T
SHDN
Rising, +20°C hysteresis
EN = low, T
J
= +25°C
EN = low, T
J
= +125°C
SKIP mode, no switching,
T
J
= -40° to +85°C
FPWM mode, no load
2.30
0.1
1
55
6
100
+165
70
5.50
V
µA
µA
mA
Ω
°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply Current
Output Voltage Accuracy
Load Transient Response
Output Voltage Ramp-Up
Slew Rate
Output Voltage Ramp-Down
Slew Rate
Typical Condition
Efficiency
Peak Efficiency
50
20
40
5
10
95
97
4.50
1.80
40
55
2.50
2.75
5.70
2.65
mV
mV/µs
mV/µs
%
%
A
mΩ
mΩ
MHz
www.maximintegrated.com
Maxim Integrated
│
3
MAX77813
High-Efficiency Buck-Boost Converter
Buck-Boost Electrical Characteristics (continued)
(V
SYS
= V
INBB
= +3.8V, V
FB_BB
= V
OUTBB
= +3.3V, T
J
= -40°C to +125°C, typical values are at T
A
≈ T
J
= +25°C, unless otherwise
noted.) (Note 4)
PARAMETER
Turn-On Delay Time
Soft-Start Time
Minimum Effective Output
Capacitance
LXBB1, LXBB2 Leakage
Current
POWER-OK COMPARATOR
Output POK Trip Level
V
SYS
UNDERVOLTAGE LOCKOUT
V
SYS
Undervoltage Lockout
Threshold
LOGIC AND CONTROL INPUTS
Input Low Level
Input High Level
POK Output Low Voltage
POK Output High Leakage
V
IL
V
IH
V
OL
I
OZH_25C
I
OZH_125C
R
PD
EN, ILIM, V
SYS
= 3.8V, T
J
= +125°C
EN, ILIM, V
SYS
= 3.8V, T
J
= -40°C
I
SINK
= 1mA
T
J
= +25°C
T
J
= +125°C
Pulldown resistance to GND
400
-1
0.1
800
1600
1.2
0.4
+1
0.4
V
V
V
µA
V
UVLO_R
V
UVLO_F
V
SYS
rising
V
SYS
falling
2.375
2.50
2.05
2.625
V
Rising threshold
Falling threshold
80
75
%
SYMBOL
t
ON_DLY
t
SS
C
EFF(MIN)
I
LK_25C
I
LK_125C
CONDITIONS
From EN asserting to LXBB switching with
bias ON
I
OUT
= 10mA, ILIM = high
I
OUT
= 10mA, ILIM = low
0A < I
OUT
< 2000mA
V
LXBB1/2
= 0V or 5.5V, V
OUTBB
= 5.5V,
V
SYS
= V
INBB
= 5.5V, T
J
= +25°C
V
LXBB1/2
= 0V or 5.5V, V
OUTBB
= 5.5V,
V
SYS
= V
INBB
= 5.5V, T
J
= +125°C
MIN
TYP
100
120
800
16
0.1
0.2
1
µA
MAX
UNITS
µs
µs
µF
INTERNAL PULLDOWN RESISTANCE
EN
kΩ
Note 2:
Limits are 100% production tested at T
J
= +25°C. The device is tested under pulsed load conditions such that T
J
≈ T
A.
Limits over the operating temperature range are guaranteed through correlation using statistical quality control methods.
Note 3:
Guaranteed by design. Not production tested.
www.maximintegrated.com
Maxim Integrated
│
4
MAX77813
High-Efficiency Buck-Boost Converter
I
2
C Electrical Characteristics
(V
SYS
= 3.8V, V
VIO
= 1.8V, T
J
= -40°C to +125°C, typical values are at T
A
≈ T
J
= +25°C, unless otherwise noted.) (Note 4)
PARAMETER
POWER SUPPLY
V
IO
Voltage Range
SDA AND SCL I/O STAGES
SCL, SDA Input High Voltage
SCL, SDA Input Low Voltage
SCL, SDA Input Hysteresis
SCL, SDA Input Current
SDA Output Low Voltage
SCL, SDA Input Capacitance
Output Fall Time from V
VIO
to
0.3 x V
VIO
Clock Frequency
Hold Time (REPEATED)
START Condition
SCL Low Period
SCL High Period
Setup Time REPEATED
START Condition
DATA Hold Time
DATA Setup Time
Setup Time for STOP
Condition
Bus-Free Time Between
STOP and START
Capacitive Load for Each
Bus Line
Maximum Pulse Width
of Spikes that must be
suppressed by the input filter
V
IH
V
IL
V
HYS
I
I
V
OL
C
I
t
OF
V
VIO
= 3.8V
I
SINK
= 20mA
10
120
-10
0.05 x
V
VIO
+10
0.4
0.7 x
V
VIO
0.3 x
V
VIO
V
V
V
µA
V
pF
ns
V
VIO
1.7
3.6
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
2
C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST-MODE PLUS) (Note 5)
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