Programmable High-g Digital
Impact Sensor and Recorder
ADIS16204
FEATURES
Dual-axis sensing, ±70
g,
±37
g
14-bit resolution
Impact peak-level sample-and-hold
RSS output
Programmable event recorder
400 Hz double-pole Bessel sensor response
Digitally controlled sensitivity and bias
Digitally controlled sample rate, up to 4096 SPS
Programmable condition monitoring alarms
Auxiliary digital I/O
Digitally activated self-test
Embedded temperature sensor
Programmable power management
SPI-compatible serial interface
Auxiliary 12-bit ADC input and DAC output
Single-supply operation: +3.0 V to +3.6 V
4000
g
powered shock survivability
FUNCTIONAL BLOCK DIAGRAM
AUX
ADC
AUX
DAC VREF
ADIS16204
TEMPERATURE
SENSOR
INERTIAL
MEMS
SENSOR
CS
DIGITAL
PROCESSING
SPI
PORT
SCLK
DIN
SIGNAL
CONDITIONING
AND
CONVERSION
TE
SELF-TEST
DIGITAL
CONTROL
VDD
POWER
MANAGEMENT
ALARMS
COM
RST
DOUT
AUXILIARY
I/O
EVENT
CAPTURE
BUFFER
MEMORY
06448-001
DIO1 DIO2
Figure 1.
APPLICATIONS
Crash or impact detection
Condition monitoring of valuable goods
Safety, shut-off sensing
Impact event recording
Security sensing, tamper detection
GENERAL DESCRIPTION
The ADIS16204 is a fully-contained programmable impact
sensor in a single compact package enabled by the Analog
Devices, Inc.
iSensor™
integration. By enhancing the Analog
Devices
iMEMS®
sensor technology with an embedded signal
processing solution, the ADIS16204 provides tunable digital
sensor data in a convenient format that can be accessed using
a serial peripheral interface (SPI). The SPI provides access to
measurements for dual-axis linear acceleration, a root sum
square (RSS) of both axes, temperature, power supply, an
auxiliary analog input, and an event capture buffer memory. Easy
access to digital sensor data provides users with a system-ready
device, reducing development time, cost, and program risk.
SO
B
O
Unique characteristics of the end system are accommodated
easily through several built-in features, such as a single command
in-system bias null/offset calibration, along with convenient
sample rate control.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
LE
The ADIS16204 offers the following embedded features, which
eliminate the need for external circuitry and provide a simplified
system interface:
Peak sample-and-hold
Programmable event recording (dual, 1K × 16 bit)
RSS output (total shock in the XY plane)
Configurable alarms
Auxiliary 12-bit ADC and DAC
Configurable digital I/O port
Digital self-test function
The ADIS16204 offers two power management features for
managing system-level power dissipation: low power mode
and a configurable shutdown feature.
The ADIS16204 is available in a 9.2 mm × 9.2 mm × 3.9 mm
laminate-based land grid array (LGA) package with a tem-
perature range of −40°C to +105°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
ADIS16204
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Recommended Pad Geometry.................................................... 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 10
Overview...................................................................................... 10
Temperature Sensor ................................................................... 10
Acceleration Sensor .................................................................... 10
Impact/Shock Response ............................................................ 10
Auxiliary ADC Function ........................................................... 11
Basic Operation .............................................................................. 12
Serial Peripheral Interface ......................................................... 12
Data Output Register Access .................................................... 13
Programming and Control ............................................................ 14
Control Register Overview ....................................................... 14
Control Register Structure ........................................................ 14
Calibration................................................................................... 15
Operational Control................................................................... 16
Status and Diagnostics ............................................................... 17
Alarm Detection and Event Capture ....................................... 18
Second-Level Assembly ................................................................. 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
Global Commands ..................................................................... 15
REVISION HISTORY
10/07—Rev. 0 to Rev. A
Changes to Power Supply Current Specification .......................... 4
Changes to Overview Section ....................................................... 10
6/07—Revision 0: Initial Version
O
Rev. B | Page 2 of 24
B
SO
12/09—Rev. A to Rev. B
Changes to Figure 23 ...................................................................... 13
LE
TE
ADIS16204
SPECIFICATIONS
T
A
= −40
o
C to +105°C, VDD = 3.3 V, unless otherwise noted.
Table 1.
Parameter
ACCELEROMETER
Output Full-Scale Range
Sensitivity
Nonlinearity
Sensor-to-Sensor Alignment Error
Cross-Axis Sensitivity
Resonant Frequency
OFFSET
Zero-g Output
1
NOISE
Noise Density
FREQUENCY RESPONSE
Sensor Bandwidth (−3 dB)
Temperature Drift
ACCELEROMETER SELF-TEST STATE
2
Output Change When Active
Output Change When Active
TEMPERATURE SENSOR
Output at 25°C
Scale Factor
ADC INPUT
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Gain Error
Input Range
Input Capacitance
ON-CHIP VOLTAGE REFERENCE
Accuracy
Reference Temperature Coefficient
Output Impedance
DAC OUTPUT
Resolution
Relative Accuracy
Differential Nonlinearity (DNL)
Offset Error
Gain Error
Output Range
Output Impedance
Output Settling Time
Conditions
Axis
X
Y
X
Y
Min
±70
±37
17.125
8.407
0.2
0.1
−5
+5
24
Typ
Max
Unit
g
g
mg/LSB
mg/LSB
%
Degrees
%
kHz
g
g
mg/√Hz
440
Hz
Hz
LSB
LSB
LSB
LSB/°C
Bits
LSB
LSB
LSB
LSB
V
pF
V
mV
ppm/
o
C
Ω
Bits
LSB
LSB
mV
%
V
Ω
μs
10 Hz − 400 Hz, no postfiltering
2-pole Bessel
|25°C − T
MIN
| or |T
MAX
− 25°C|
At 25°C
LE
X
Y
Rev. B | Page 3 of 24
SO
0
During acquisition
At 25°C
−10
5 kΩ/100 pF to GND
For Code 101 to Code 4095
B
TE
X
Y
0.2
0.2
1.8
360
400
2
254
518
1278
−2.13
12
±2
±1
±4
±2
20
2.5
±40
70
12
4
1
±5
±0.5
0 to 2.5
2
10
2.5
O
+10
ADIS16204
Parameter
LOGIC INPUTS
3
Input High Voltage, V
INH
Input Low Voltage, V
INL
Logic 1 Input Current, I
INH
Logic 0 Input Current, I
INL
Input Capacitance, C
IN
DIGITAL OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
SLEEP TIMER
Timeout Period
4
START-UP TIME
Initial
Reset recovery
FLASH MEMORY
Endurance
5
Data Retention
6
CONVERSION RATE
Maximum Throughput Rate
Minimum Throughput Rate
POWER SUPPLY
Operating Voltage Range, VDD
Power Supply Current
Conditions
Axis
Min
2.0
V
IH
= VDD
V
IL
= 0 V
±0.2
−40
10
2.4
0.4
0.5
128
130
2.5
0.8
±1
−60
Typ
Max
Unit
V
V
μA
μA
pF
V
V
Seconds
ms
ms
Cycles
Years
SPS
SPS
3.6
15
43
V
mA
mA
μA
I
SOURCE
= 1.6 mA
I
SINK
= 1.6 mA
T
J
= 85°C
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Rev. B | Page 4 of 24
SO
Normal mode, SMPL_PRD ≥ 0x08
(f
S
≤ 910 Hz), at 25°C
Fast mode, SMPL_PRD ≤ 0x07
(f
S
≥ 1024 Hz), at 25°C
Sleep mode, at 25°C
1
2
3
4
5
6
Note that gravity can impact this number; zero-g condition assumes both axes oriented normal to the earth’s gravity.
Self-test response changes as the square of VDD.
Note that the inputs are +5 V tolerant.
Guaranteed by design.
Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +105°C.
Retention lifetime equivalent at junction temperature (T
J
), 55°C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature.
O
B
TE
20,000
20
4096
2.066
3.0
3.3
12
37
150
ADIS16204
TIMING SPECIFICATIONS
T
A
= +25°C, V
CC
= +3.3 V, unless otherwise noted.
Table 2.
Parameter
f
SCLK
t
DATARATE
t
CSHIGH
t
CS
t
DAV
t
DSU
t
DHD
t
DF
t
DR
t
SFS
1
2
Guaranteed by design; typical specifications are not tested or guaranteed.
Based on sample rate selection.
CS
LE
t
DATARATE
SCLK
CS
t
CS
SCLK
SO
1
2
3
4
5
Figure 2. SPI Chip Select Timing
06448-002
TE
5
5
5
6
15
16
DB11
DB10
DB2
DB1
LSB
A3
A2
D2
D1
LSB
Description
Fast mode
2
Normal mode
2
Chip select period, fast mode
2
Chip select period, normal mode
2
Chip select high
Chip select to clock edge
Data output valid after SCLK edge
Data input setup time before SCLK rising edge
Data input hold time after SCLK rising edge
Data output fall time
Data output rise time
CS high after SCLK edge
Min
1
0.01
0.01
40
100
1/f
SCLK
48.8
24.4
48.8
Typ
Max
1
2.5
1.0
Unit
MHz
MHz
μs
μs
ns
ns
ns
ns
ns
ns
ns
100
12.5
12.5
t
SFS
t
DAV
DOUT
B
MSB
DB14
DB13
DB12
t
DSU
t
DHD
A5
A4
06448-003
O
DIN
W/R
Figure 3. SPI Timing
(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
Rev. B | Page 5 of 24
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