Virtual JTAG (altera_virtual_jtag) IP
Core User Guide
Updated for Intel
®
Quartus
®
Prime Design Suite:
16.1
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Contents
Contents
Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide..............................................3
Introduction................................................................................................................ 3
Installing and Licensing Intel FPGA IP Cores........................................................... 4
On-Chip Debugging Tool Suite.............................................................................. 4
Applications of the Virtual JTAG IP Core................................................................. 5
JTAG Protocol..................................................................................................... 6
JTAG Circuitry Architecture...................................................................................7
System-Level Debugging Infrastructure.......................................................................... 9
Transaction Model of the SLD Infrastructure............................................................9
SLD Hub Finite State Machine............................................................................. 11
Virtual JTAG Interface Description.................................................................................12
Input Ports.......................................................................................................14
Output Ports.....................................................................................................14
Parameters.......................................................................................................16
Design Flow of the Virtual JTAG IP Core................................................................16
Simulation Model.............................................................................................. 17
Run-Time Communication...................................................................................18
Running a DR Shift Operation Through a Virtual JTAG Chain....................................19
Run-Time Communication............................................................................................19
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values................. 21
Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values......................22
Reset Considerations when Using a Custom JTAG Controller.................................... 23
Instantiating the Virtual JTAG IP Core........................................................................... 24
IP Catalog and Parameter Editor..........................................................................24
Specifying IP Core Parameters and Options...........................................................26
Instantiating Directly in HDL............................................................................... 27
Simulation Support.....................................................................................................29
Compiling the Design.................................................................................................. 32
Third-Party Synthesis Support.............................................................................33
SLD_NODE Discovery and Enumeration......................................................................... 33
Issuing the HUB_INFO Instruction....................................................................... 34
HUB IP Configuration Register.............................................................................35
SLD_NODE Info Register.................................................................................... 35
Capturing the Virtual IR Instruction Register.................................................................. 36
AHDL Function Prototype ............................................................................................37
VHDL Component Declaration...................................................................................... 38
VHDL LIBRARY-USE Declaration....................................................................................38
Design Example: TAP Controller State Machine............................................................... 39
Design Example: Modifying the DCFIFO Contents at Runtime........................................... 41
Write Logic.......................................................................................................41
Read Logic....................................................................................................... 42
Runtime Communication.................................................................................... 43
Design Example: Offloading Hardwired Revision Information............................................ 44
Configuring the JTAG User Code Setting............................................................... 45
Document Revision History for the Virtual JTAG (altera_virtual_jtag) IP Core User Guide......45
Virtual JTAG (altera_virtual_jtag) IP Core User Guide
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Altera Virtual JTAG (altera_virtual_jtag) IP Core User
Guide
The Altera Virtual JTAG (altera_virtual_jtag) IP core provides access to the PLD source
through the JTAG interface. This IP core is optimized for Intel
®
device architectures.
Using IP cores in place of coding your own logic saves valuable design time, and offers
more efficient logic synthesis and device implementation. You can scale the IP core's
size by setting parameters.
Related Information
Introduction to Intel FPGA IP Cores
Introduction
The Virtual JTAG IP core allows you to create your own software solution for
monitoring, updating, and debugging designs through the JTAG port without using I/O
pins on the device, and is one feature in the On-Chip Debugging Tool Suite. The Intel
Quartus
®
Prime software or JTAG control host identifies each instance of this IP core
by a unique index. Each IP core instance functions in a flow that resembles the JTAG
operation of a device. The logic that uses this interface must maintain the continuity of
the JTAG chain on behalf the PLD device when this instance becomes active.
With the Virtual JTAG IP core you can build your design for efficient, fast, and
productive debugging solutions. Debugging solutions can be part of an evaluation test
where you use other logic analyzers to debug your design, or as part of a production
test where you do not have a host running an embedded logic analyzer. In addition to
debugging features, you can use the Virtual JTAG IP core to provide a single channel
or multiple serial channels through the JTAG port of the device. You can use serial
channels in applications to capture data or to force data to various parts of your logic.
Each feature in the On-Chip Debugging Tool Suite leverages on-chip resources to
achieve real time visibility to the logic under test. During runtime, each tool shares the
JTAG connection to transmit collected test data to the Intel Quartus Prime software for
analysis. The tool set consists of a set of GUIs, IP core intellectual property (IP) cores,
and Tcl application programming interfaces (APIs). The GUIs provide the configuration
of test signals and the visualization of data captured during debugging. The Tcl
scripting interface provides automation during runtime.
The Virtual JTAG IP core provides you direct access to the JTAG control signals routed
to the FPGA core logic, which gives you a fine granularity of control over the JTAG
resource and opens up the JTAG resource as a general-purpose serial communication
interface. A complete Tcl API is available for sending and receiving transactions into
your device during runtime. Because the JTAG pins are readily accessible during
runtime, this IP core enables an easy way to customize a JTAG scan chain internal to
the device, which you can then use to create debugging applications.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered
Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide
UG-SLDVRTL | 2018.07.19
Examples of debugging applications include induced trigger conditions evaluated by a
Signal Tap logic analyzer by exercising test signals connected to the analyzer instance,
a replacement for a front panel interface during the prototyping phase of the design,
or inserted test vectors for exercising the design under test.
The infrastructure is an extension of the JTAG protocol for use with Intel-specific
applications and user applications, such as the Signal Tap logic analyzer.
Installing and Licensing Intel FPGA IP Cores
The Intel Quartus Prime software installation includes the Intel FPGA IP library. This
library provides many useful IP cores for your production use without the need for an
additional license. Some Intel FPGA IP cores require purchase of a separate license for
production use. The Intel FPGA IP Evaluation Mode allows you to evaluate these
licensed Intel FPGA IP cores in simulation and hardware, before deciding to purchase a
full production IP core license. You only need to purchase a full production license for
licensed Intel IP cores after you complete hardware testing and are ready to use the
IP in production.
The Intel Quartus Prime software installs IP cores in the following locations by default:
Figure 1.
IP Core Installation Path
intelFPGA(_pro)
quartus -
Contains the Intel Quartus Prime software
ip -
Contains the Intel FPGA IP library and third-party IP cores
altera -
Contains the Intel FPGA IP library source code
<IP name>
- Contains the Intel FPGA IP source files
Table 1.
IP Core Installation Locations
Location
Software
Intel Quartus Prime Pro Edition
Intel Quartus Prime Standard
Edition
Intel Quartus Prime Pro Edition
Intel Quartus Prime Standard
Edition
Platform
Windows*
Windows
Linux*
Linux
<drive>:\intelFPGA_pro\quartus\ip\altera
<drive>:\intelFPGA\quartus\ip\altera
<home directory>:/intelFPGA_pro/quartus/ip/altera
<home directory>:/intelFPGA/quartus/ip/altera
On-Chip Debugging Tool Suite
The On-Chip Debugging Tool Suite enables real time verification of a design and
includes the following tools:
Virtual JTAG (altera_virtual_jtag) IP Core User Guide
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Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide
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Table 2.
Tool
On-Chip Debugging Tool Suite
Description
Uses FPGA resources to sample tests nodes
and outputs the information to the Intel
Quartus Prime software for display and
analysis.
Incrementally routes internal signals to I/O
pins while preserving the results from your
last place-and-route.
Multiplexes a larger set of signals to a
smaller number of spare I/O pins. LAI allows
you to select which signals are switched
onto the I/O pins over a JTAG connection.
Displays and allows you to edit on-chip
memory.
Provides a way to drive and sample logic
values to and from internal nodes using the
JTAG interface.
Opens the JTAG interface so that you can
develop your own custom applications.
Typical Circumstances for Use
You have spare on-chip memory and want functional
verification of your design running in hardware.
Signal Tap Logic
Analyzer
Signal Probe
You have spare I/O pins and want to check the
operation of a small set of control pins using either an
external logic analyzer or an oscilloscope.
You have limited on-chip memory and have a large set
of internal data buses that you want to verify using an
external logic analyzer. Logic analyzer vendors, such as
Tektronics and Agilent, provide integration with the tool
to improve usability.
You want to view and edit the contents of either the
instruction cache or data cache of a Nios
®
II processor
application.
You want to prototype a front panel with virtual
buttons for your FPGA design.
You want to generate a large set of test vectors and
send them to your device over the JTAG port to
functionally verify your design running in hardware.
Logic Analyzer
Interface (LAI)
In-System
Memory
Content Editor
In-System
Sources and
Probes
Virtual JTAG
Interface
Related Information
System Debugging Tools Overview
Applications of the Virtual JTAG IP Core
You can instantiate single or multiple instances of the Virtual JTAG IP core in your HDL
code. During synthesis, the Intel Quartus Prime software assigns unique IDs to each
instance, so that each instance is accessed individually. You can instantiate up to 128
instances of the Virtual JTAG IP core. The figure below shows a typical application in a
design with multiple instances of the IP core.
Virtual JTAG (altera_virtual_jtag) IP Core User Guide
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