Agenda
LPC2900 Overview and Development tools
Control of BLDC Motors using the LPC2900
CPU Load of BLDCM and PMSM
Enhancing performance
LPC2900 Demo BLDC motor
2
LPC2900 Summary
ARM968E core
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125 MHz operation
Vectored Interrupt Controller
Power Management Unit
Clock Generation Unit
Embedded Trace with 8 KB buffer
Up to 768 KB Flash
Up to 48 KB SRAM (+ 8KB)
Up to 32 KB I- & D- TCM
16 KB EEPROM (Byte)
External Memory Controller
Serial Peripherals
– USB 2.0 full-speed device/Host/OTG
controller with on-chip PHY
– Two LIN 2.0 master controllers
– Up to four UARTs with baud rate
generation, LIN and RS-485 support
– Two CAN 2.0B controllers
– Three Q-SPI controllers
– Two I
2
C-bus interfaces
Memories
Other Peripherals
– General Purpose DMA controller
– Motor control PWM and Quadrature
Encoder Interface to support three-
phase motors
– Six 32-bit timers
– Up to 148 General Purpose I/O
Analog Peripherals
– Two 3.3 V 10-bit/8-ch ADC’s
– One 5V 10-bit/8-ch ADC’s
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嵌入式系统
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