NCP81274
8/7/6/5/4/3/2/1 Phase Buck
Controller with PWM_VID
and I
2
C Interface
The NCP81274 is a multiphase synchronous controller optimized
for new generation computing and graphics processors. The device is
capable of driving up to 8 phases and incorporates differential voltage
and phase current sensing, adaptive voltage positioning and
PWM_VID interface to provide and accurately regulated power for
computer or graphic controllers. The integrated power saving
interface (PSI) allows for the processors to set the controller in one of
three modes, i.e. all phases on, dynamic phases shedding or fixed low
phase count mode, to obtain high efficiency in light-load conditions.
The dual edge PWM multiphase architecture ensures fast transient
response and good dynamic current balance.
Features
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1
40
QFN40
CASE 485CR
MARKING DIAGRAM
1
ON
NCP
81274
AWLYYWWG
G
NCP81274 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb-Free Package
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Compliant with NVIDIA
®
OVR4+ Specifications
Supports Up to 8 Phases
4.5 V to 20 V Supply Voltage Range
250 kHz to 1.2 MHz Switching Frequency (8 Phase)
Power Good Output
Under Voltage Protection (UVP)
Over Voltage Protection (OVP)
Over Current Protection (OCP)
Per Phase Over Current Protection
Startup into Pre-Charged Loads while Avoiding False OVP
Configurable Adaptive Voltage Positioning (AVP)
High Performance Operational Error Amplifier
True Differential Current Balancing Sense Amplifiers for Each
Phase
Phase-to-Phase Dynamic Current Balancing
Current Mode Dual Edge Modulation for Fast Initial Response to
Transient Loading
Power Saving Interface (PSI)
Automatic Phase Shedding with User Settable Thresholds
PWM_VID and I
2
C Control Interface
Compact 40 Pin QFN Package (5
×
5 mm Body, 0.4 mm Pitch)
This Device is Pb-Free and is RoHS Compliant
PIN CONNECTIONS
VID_BUFF
PWM_VID
PGOOD
SDA
VCC
33
VSN
32
36
40
38
39
37
35
34
31
VSP
SCL
PSI
EN
REFIN
VREF
VRMP
PWM8/SS
PWM7/OCP
PWM6/LPC1
PWM5/LPC2
PWM4/PHTH1
PWM3/PHTH2
PWM2/PHTH3
1
2
3
4
5
6
7
8
9
10
12
11
13
14
15
16
17
18
19
20
30
29
28
COMP
FB
DIFF
FSW
LLTH/I2C_ADD
IOUT
ILIM
CSCOMP
CSSUM
CSREF
NCP81274
(TOP VIEW)
Tab: GROUND
27
26
25
24
23
22
21
CSP4
CSP7
CSP6
PWM1/
PHTH4
DRON
Typical Applications
•
GPU and CPU Power
•
Graphic Cards
•
Desktop and Notebook Applications
ORDERING INFORMATION
Device
NCP81274MNTXG
Package
QFN40
(Pb-Free)
Shipping
†
5000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure,
BRD8011/D.
©
Semiconductor Components Industries, LLC, 2017
1
CSP8
June, 2017 − Rev. 14
Publication Order Number:
NCP81274/D
CSP5
CSP3
CSP2
CSP1
TP45 TP46 TP47 TP48 TP49
TP50
TP51
VCC_DUT
VSN_sense
J4
C5
J3
C17
1000pF
SDA
SCL
EN
PSI
PGOOD
1uF
R38
2.2R
PWM_VID in
J1
C2
R37
TP52
R28
R25
4.32k
20.5k
4.7nF
TP44
6.19k
TP53
TP54
TP1
VSP_sense
TP36
TP37
40
39
38
37
36
35
34
33
32
R21
16.5k
31
TP42
C15
R43
9.69k
C18
R9
R16
309R
REFIN
U1
PSI
EN
SCL
SDA
VCC
VSN
VSP
2.2nF
C16
R49
TP38
TP43
1k
C4
4.7nF
C3
VIN
1
REFIN
VREF
VRAMP
PWM8/SS
PWM7/OCP
PWM6/LPC1
PWM5/LPC2
PWM4/PHTH1
PWM3/PHTH2
PWM2/PHTH3
CSREF
DRON
CSP8
CSP7
CSP6
CSP5
CSP4
CSP3
CSP2
CSP1
41
PWM1/PHTH4
PAD
11
12
13
14
15
16
17
18
19
R4
10k
R7
10k
R13
1k
R10
10k
R14
1k
TP62
R18
33k
R22
68k
TP39
PGOOD
VID_BUFF
PWM_VID
TP41
TP40
VREF
10nF
COMP
FB
DIFF
FSW
27
26
25
24
23
22
21
28
29
68pF
30
49.9R
680pF
R48
1k
TP55
TP56
TP57
TP58 TP59
C1
0.01uF
2
3
4
5
6
IOUT
ILIM
CSCOMP
CSSUM
7
8
9
10
PWM8
PWM7
PWM6
NCP81274
LLTH/I2C ADD
R124
0R
PWM2
R55
47k
R5610k
R54
R50
20
NCP81274
10R
R51
R2
10k
R39
10R
RT1 220k
C13
390nF
75k
R40
R1 DNP
R41
R42
R44
R5 DNP
R6 DNP
R8 DNP
R11 DNP
R12 DNP
C8 0.1uF
C9 0.1uF
C10 0.1uF
C11 0.1uF
C12 0.1uF
C14
R152k32
R19 2k32
R17 2k32
R24 2k32
10R
R3 DNP
C7 0.1uF
10R
VCC_DUT
1
R45
10R
TP60
R46
10R
2
R20 2k32
R23 2k32
R26 2k32
R27 2k32
R1420R
R144 0R
R143 0R
R148 0R
R36 215k
CSN6
CSN3
CSN2
SWN7
SWN6
SWN5
SWN8
SWN4
SWN3
SWN2
SWN1
CSN8
CSN7
CSN5
CSN4
CSN1
R32 215k
R145 0R
R146 0R
R147 R
0
R149 0R
Figure 1. Typical Controller Application Circuit
R47
10R
TP61
0.1uF
R30 215k
R29 215k
R31 215k
R33 215k
R34 215k
R35 215k
1000pF
C6
0.1uF
10R
C20 36pF
DRON
165k
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C19
51k
R57 26.1k
1
PWM1
R1270R
R1260R
PWM3
R1250R
PWM4
C21 470pF
PWM5
2
VIN
+
C95
R69
2.2R
TP64
C32
0.1uF
C65
10uF
C39
10uF
C47
10uF
C52
10uF
C57
10uF
C75
10uF
C85
10uF
56uF
TP87
C27
0.22uF
3
4
9
U2
1
BST
PWM
SW
7
HG
8
2
NCP81161
R60 0R
L1
0.22uH
3
4
9
TP65
VOUT
PWMx
SW
SW
3
EN
VCC
PAD
LG
5
4
GND 6
1
G1
2
S1
DRON
7
6
5
8
G2
R75
DNP
S2
1
G1
2
S1
7
6
5
NCP81274
Figure 2. Typical Phase Application Circuit
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8
G2
Q1
S2
C22
4.7uF
10
10
3
Q6
C37
DNP
NTMFD4C85N
NTMFD4C85N
TP63
R59 0R
VCC_DRV
+
C62
+
C72
+
C82
+
C92
R133 0R
330uF
330uF
DNP
DNP
C102
22uF
C107
22uF
C112
22uF
C117
22uF
R82
1
2
SHORTPIN
R83
CSNx
1
2
SHORTPIN
SWNx
NCP81274
Table 1. PIN FUNCTION DESCRIPTION
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin
Name
REFIN
VREF
VRMP
PWM8/SS
PWM7/OCP
PWM6/LPC1
PWM5/LPC2
PWM4/PHTH1
PWM3/PHTH2
PWM2/PHTH3
PWM1/PHTH4
DRON
CSP8
CSP7
CSP6
CSP5
CSP4
CSP3
CSP2
CSP1
CSREF
CSSUM
CSCOMP
ILIM
IOUT
LLTH/I2C_ADD
FSW
DIFF
Pin
Type
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
O
O
O
I
I
O
Description
Reference voltage input for output voltage regulation.
2.0 V output reference voltage. A 10 nF ceramic capacitor is required to connect this pin
to ground.
Feed-forward input of VIN for the ramp slope compensation. The current fed into this pin
is used to control of the ramp of PWM slope.
PWM 8 output/Soft Start setting. During startup it is used to program the soft start time
with a resistor to ground.
PWM 7 output/Per OCP setting. During startup it is used to program the OCP level per
phase and latch off time with a resistor to ground.
PWM 6 output/Low phase count 1. During startup it is used to program the power zone
(PSI set low) with a resistor to ground.
PWM 5 output/Low phase count 2. During startup it is used to program boot-up power
zone (PSI set low) with a resistor to ground.
PWM 4 output/Phase Shedding Threshold 1. During startup it is used to program the
phase shedding threshold 1 (PSI set to mid state) with a resistor to ground.
PWM 3 output/Phase Shedding Threshold 2. During startup it is used to program the
phase shedding threshold 2 (PSI set to mid state) with a resistor to ground.
PWM 2 output/Phase Shedding Threshold 3. During startup it is used to program the
phase shedding threshold 3 (PSI set to mid state) with a resistor to ground.
PWM 1 output/Phase Shedding Threshold 4. During startup it is used to program the
phase shedding threshold 4 (PSI set to mid state) with a resistor to ground.
Bidirectional gate driver enable for external drivers.
Non-inverting input to current balance sense amplifier for phase 8. Pull-up to VCC to
disable the PWM8 output.
Non-inverting input to current balance sense amplifier for phase 7. Pull-up to VCC to
disable the PWM7 output.
Non-inverting input to current balance sense amplifier for phase 6. Pull-up to VCC to
disable the PWM6 output.
Non-inverting input to current balance sense amplifier for phase 5. Pull-up to VCC to
disable the PWM5 output.
Non-inverting input to current balance sense amplifier for phase 4. Pull-up to VCC to
disable the PWM4 output.
Non-inverting input to current balance sense amplifier for phase 3. Pull-up to VCC to
disable the PWM3 output.
Non-inverting input to current balance sense amplifier for phase 2. Pull-up to VCC to
disable the PWM2 output.
Non-inverting input to current balance sense amplifier for phase 1. Pull-up to VCC to
disable the PWM1 output.
Total output current sense amplifier reference voltage input.
Inverting input of total current sense amplifier.
Output of total current sense amplifier.
Over current shutdown threshold setting output. The threshold is set by a resistor
between ILIM and to CSCOMP pins.
Total output current. A resistor to GND is required to provide a voltage drop of 2 V at the
maximum output current.
Load line selection from 0% to 100% and I
2
C address pin.
Resistor to ground form this pin sets the operating frequency of the regulator.
Output of the regulators differential remote sense amplifier.
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4
NCP81274
Table 1. PIN FUNCTION DESCRIPTION
(continued)
Pin
Number
29
30
31
32
33
34
35
36
37
38
39
40
41
Pin
Name
FB
COMP
VSP
VSN
VCC
SDA
SCL
EN
PSI
PGOOD
PWM_VID
VID_BUFF
AGND
Pin
Type
I
O
I
I
I
I/O
I
I
I
O
I
O
GND
Description
Error amplifier inverting (feedback) input.
Output of the error amplifier and the inverting input of the PWM comparator.
Differential Output Voltage Sense Positive terminal.
Differential Output Voltage Sense Negative terminal.
Power for the internal control circuits. A 1
mF
decoupling capacitor is requires from this
pin to ground.
Serial Data bi-directional pin, requires pull-up resistor to VCC.
Serial Bus clock pin, requires pull-up resistor to VCC.
Logic input. Logic high enables regulator output logic low disables regulator output.
Power Saving Interface control pin. This pin can be set low, high or left floating.
Use a current limiting resistor of 100 kW when driving the pin with 5 V logic.
Open Drain power good indicator.
PWM_VID buffer input.
PWM_VID pulse output from internal buffer.
Analog ground and thermal pad, connected to system ground.
Table 2. MAXIMUM RATINGS
Rating
Pin Voltage Range (Note 1)
Pin Symbol
VSN
VCC
VRMP
PWM_VID
All Other Pins
with the
exception of
the DRON Pin
Pin Current Range
COMP
CSCOMP
DIFF
PGOOD
VSN
Moisture Sensitivity Level
Lead Temperature Soldering Reflow (SMD Styles Only),
Pb-Free Versions (Note 2)
MSL
T
SLD
−1
1
260
1
mA
−
°C
Min
GND−0.3
−0.3
−0.3
−0.3
(−2, < 50 ns)
−0.3
Typ
Max
GND + 0.3
6.5
25
VCC + 0.3
VCC + 0.3
Unit
V
V
V
V
V
−2
2
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All signals referenced to GND unless noted otherwise.
2. For information, please refer to our Soldering and Mounting Techniques Reference Manual,
SOLDERRM/D.
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