FEDR48V256C-01
Issue Date: Nov. 13, 2013
MR48V256C
32,768-Word
8-Bit FeRAM (Ferroelectric Random Access Memory)
GENERAL DESCRIPTION
The MR48V256C is a nonvolatile 32,768-word x 8-bit ferroelectric random access memory (FeRAM) developed
in the ferroelectric process and silicon-gate CMOS technology. Unlike SRAMs, this device, whose cells are
nonvolatile, eliminates battery backup required to hold data. This device has no mechanisms of erasing and
programming memory cells and blocks, such as those used for various EEPROMs. Therefore, the write cycle
time can be equal to the read cycle time and the power consumption during a write can be reduced significantly.
The MR48V256C can be used in various applications, because the device is guaranteed for the write/read
tolerance of 10
12
cycles per bit and the rewrite count can be extended significantly.
FEATURES
•
•
•
•
•
•
•
•
•
32,768-word
8-bit configuration
A single 2.7 to 3.6V power supply
Read access time:
70 ns (Max.)
Write enable time:
70 ns (Min.)
Random read/write cycle time
150 ns (Min.)
Read/write tolerance
10
12
cycles/bit
Data retention
10 years
Guaranteed operating temperature range
40
to 85C (Extended temperature version)
Package options:
28-pin plastic TSOPI (TSOP(1)28-08134-0.55-ZK6)
PRODUCT FAMILY
Family
Access Time
Relative to CE
MR48V256C
70ns
Relative to OE
40ns
Read/Write
Cycle Time
150ns
Package
28pin TSOPI
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FEDR48V256C-01
MR48V256C
PIN CONFIGURATION
28-pin plastic TSOPI
P-TSOP(1)28-08134-0.55-ZK6
OE#
A11
A9
A8
A13
WE#
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
MR48V256C
Note:
Signal names that end with # indicate that the pins are negative-true logic.
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FEDR48V256C-01
MR48V256C
PIN DESCRIPTIONS
Pin Name
CE#
Description
Chip enable (input, negative logic)
Latches an address by low input, activates the FeRAM, and enables a read or write
operation.
Output enable (input, negative logic)
The FeRAM is in read mode when the FeRAM is active and this pin is low, and data is
output after the specified time.
Write enable (input, negative logic)
The FeRAM is in write mode when the FeRAM is active and this pin is low, and data is
capture at the timing of WE#="H" or CE#="H", whichever is earlier.
Address (input)
The FeRAM captures an address at the timing when CE#="L" is established.
3-state data bus (input/output)
Outputs data in the read mode, and captures data in the write mode.
Power supply
Apply the specified voltage to V
CC
. Connect V
SS
to ground.
OE#
WE#
A14 to A0
DQ7 to DQ0
V
CC
, V
SS
TRUTH TABLE
Operating Mode
Standby Mode
CE#
H
X
↓
Address Latched
↓
L
L
Read Mode
Write Mode
L
L
WE#
X
H
H
L
↓
H
H
L
OE#
X
H
L
H
H
↓
L
H
Note:
Having WE# and OE# “L” at the same time is forbidden.
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MR48V256C
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Pin Voltage (Input Signal)
Pin Voltage (Input/Output Voltage)
Power Supply Voltage
Storage Temperature
(Extended Temperature Version)
Operating Temperature
(Extended Temperature Version)
Power Dissipation
Allowable Input Current
Allowable Output Current
Symbol
V
IN
V
INQ
, V
OUTQ
V
CC
Tstg
Topr
P
D
I
IN
I
OUT
Rating
Min.
–0.5
–0.5
–0.5
–55
–40
1,000
±20
±20
Max.
V
CC
+ 0.5
V
CC
+ 0.5
4.6
125
85
Unit
V
V
V
°C
°C
mW
mA
mA
Ta＝25°C
Ta＝25°C
Note
Note:
The application of stress (voltage, current, or temperature) that exceeds the absolute maximum rating may
damage the device. Therefore, do not allow actual characteristics to exceed any one parameter ratings
Recommended Operating Conditions
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature (Extended
Temperature Version)
(Vss=0V)
Symbol
V
CC
V
IH
V
IL
Ta
Min.
2.7
V
CC
x 0.8
–0.3
–40
Max.
3.6
V
CC
+ 0.3
V
CC
x 0.15
85
Unit
V
V
V
°C
Note
3.3V typ.
1
2
Notes:
1. Overshoots with the pulse width of 20 ns or less and the voltage of V
CC
+ 1.0 V or less are allowed.
2. Undershoots with the pulse width of 20 ns or less and the voltage of
1.0
V or more are allowed.
3. The voltages are referenced to VSS
Capacitance
Parameter
Input Capacitance
Input/Output Capacitance
Symbol
C
IN
C
OUT
Min.
Max.
6
8
Unit
pF
pF
Note
1
1
Note:
Sampling value. Measurement conditions are V
IN
= V
OUT
= GND, f = 1MHz, and Ta = 25°C
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FEDR48V256C-01
MR48V256C
DC Characteristics
(Under recommended operating conditions)
Parameter
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Power Supply Current
(Standby)
Power Supply Current
(Operating)
Symbol
V
OH
V
OL
I
LI
I
LO
I
CCS
Condition
I
OH
= –2 mA
I
OL
= 2 mA
V
IN
= 0.2V or V
CC
–0.2V,
CE# = V
CC
–0.2V
I
OUT
= 0 mA
Read Cycle, t
RC
= Min.
V
IN
= 0.2V or V
CC
–0.2V,
CE# = 0.2V, I
OUT
= 0 mA
Min.
V
CC
0.85
–10
–10
10
10
400
µA
µA
µA
Max.
V
CC
0.15
V
Unit
V
Note
I
CCA
10
mA
1
Note:
1. Average current. Address change must be one time or less during time t
RC
.
Read/Write Cycles and Data Retention
(Under recommended operating conditions)
Parameter
Read/Write Cycle
Data Retention
Min.
10
12
10
Max.
Unit
Cycle
Year
Note
1
Notes:
1. This is applicable to the read cycle, write cycle, and CE-only cycle counts.
This is the cycle count per bit (for one address).
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