AR0230CS
1/2.7‐inch
2.1 Mp/Full HD Digital
Image Sensor
GENERAL DESCRIPTION
ON Semiconductor’s AR0230CS is a 1/2.7−inch CMOS digital
image sensor with an active−pixel array of 1928Hx1088V. It captures
images in either linear or high dynamic range modes, with a
rolling−shutter readout. It includes sophisticated camera functions
such as in−pixel binning, windowing and both video and single frame
modes. It is designed for both low light and high dynamic range scene
performance. It is programmable through a simple two−wire serial
interface. The AR0230CS produces extraordinarily clear, sharp digital
pictures, and its ability to capture both continuous video and single
frames makes it the perfect choice for a wide range of applications,
including surveillance and HD video.
Table 1. KEY PERFORMANCE PARAMETERS
Parameter
Optical Format
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Input Clock Range
Output Clock Maximum
Output
Frame
Rate
Responsivity
SNR
MAX
Max Dynamic Range
I/O
Supply
Voltage
Digital
Analog
HiSPi
Power Consumption
(typical)
Operating Temperature
Package Options
Serial
Parallel
1080p
Typical Value
1/2.7−inch (6.6 mm)
1928(H) x 1088(V) (16:9 mode)
3.0
μm
x 3.0
μm
RGB Bayer
Electronic rolling shutter and GRR
6 – 48 MHz
148.5 Mp/s (4−lane HiSPi)
74.25 Mp/s (Parallel)
HiSPi 10−, 12−, 14−, 16−, or 20−bit
10−, 12−bit
60 fps
4.0 V/lux−sec
41 dB
Up to 96 dB
1.8 or 2.8 V
1.8 V
2.8 V
0.3 V − 0.6 V (SLVS), 1.7 V − 1.9 V (HiVcm)
386 mW (Linear, 1080p30, 25°C, parallel output)
558 mW (HDR, 1080p30, 25°C, parallel output)
–30°C to +85°C ambient
10x10 mm 80−pin iBGA
www.onsemi.com
IBGA80 10
y
10
CASE 503AN
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
•
Superior low−light performance
•
Latest 3.0
μm
pixel with ON Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DR−Pix™ technology with Dual Conversion
Gain
Full HD support at up to 1080P 60 fps for
superior video performance
Linear or high dynamic range capture
Optional adaptive local tone mapping
(ALTM)
Pixel or Line interleaved T1/T2 output
Support for external mechanical shutter
On−chip phase−locked loop (PLL) oscillator
Integrated position−based color and lens
shading correction
Slave mode for precise frame−rate control
Stereo/3D camera support
Statistics engine
Data interfaces: four−lane serial high−speed
pixel interface (HiSPi) differential signaling
(SLVS and HiV
CM
), or parallel
Auto black level calibration
High−speed configurable context switching
Temperature sensor
Features
Applications
•
Video surveillance
•
1080p60 (Surveillance) video applications
•
High dynamic range imaging
©
Semiconductor Components Industries, LLC, 2006
1
August, 2017 − Rev.11
Publication Order Number:
AR0230CS/D
AR0230CS
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
AR0230CSSC00SUEA0−DRBR
AR0230CSSC00SUEAH3−GEVB
AR0230CSSC12SUEA0−DR
AR0230CSSC12SUEAH3−GEVB
Product Description
2 Mp 1/3” CIS RGB, 0deg CRA, iBGA Package
RGB, 0deg CRA, Headboard
2 Mp 1/3” CIS RGB, 12deg CRA, iBGA Package
RGB, 12deg CRA, Headboard
Orderable Product Attribute De-
scription †
Drypack, Anti−Reflective Glass
Headboard
Drypack
Headboard
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
See the ON Semiconductor Device Nomenclature
document (TND310/D) for a full description of the naming
convention used for image sensors. For reference
GENERAL DESCRIPTION
The ON Semiconductor AR0230CS can be operated in its
default mode or programmed for frame size, exposure, gain,
and other parameters. The default mode output is a
1080p−resolution image at 60 frames per second (fps)
through the HiSPi port. In linear mode, it outputs 12−bit or
10−bit A−Law compressed raw data, using either the parallel
or serial (HiSPi) output ports. In high dynamic range mode,
it outputs 12−bit compressed data using parallel output. In
HiSPi mode, 12− or 14−bit compressed, or 16−bit linearized
data may be output. The device may be operated in video
(master) mode or in single frame trigger mode.
FUNCTIONAL OVERVIEW
The AR0230CS is a progressive−scan sensor that
generates a stream of pixel data at a constant frame rate. It
uses an on−chip, phase−locked loop (PLL) that can be
optionally enabled to generate all internal clocks from a
single master input clock running between 6 and 48 MHz.
documentation, including information on evaluation kits,
please visit our web site at
www.onsemi.com.
FRAME_VALID and LINE_VALID signals are output on
dedicated pins, along with a synchronized pixel clock in
parallel mode.
The AR0230CS includes additional features to allow
application−specific tuning: windowing and offset, auto
black level correction, and on−board temperature sensor.
Optional register information and histogram statistic
information can be embedded in the first and last 2 lines of
the image frame.
The AR0230CS is designed to operate over a wide
temperature range of −30°C to +85°C ambient.
The maximum output pixel rate is 148.5 Mp/s,
corresponding to a clock rate of 74.25 MHz. Figure 1 shows
a block diagram of the sensor configured in linear mode, and
in HDR mode.
www.onsemi.com
2
AR0230CS
ADC Data
12
ADC Data
12
Row Noise Correction
Black Level Correction
Test Pattern Generator
Pixel Defect Correction
Adaptive CD Filter
12
Row Noise Correction
Black Level Correction
Test Pattern Generator
Pixel Defect Correction
Adaptive CD Filter
12
Digital Gain and Pedestal
Digital Gain and Pedestal
Motion Correction
A−Law Compression
10 bits
12 bits
HISPI
Parallel
HDR Linearization
Smoothing Filter
16
16 bits
Companding or ALTM
14 or 12 bits
HISPI
12 bits
Parallel
Figure 1. Block Diagram of AR0230CS
User interaction with the sensor is through the two−wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 2.1 Mp Active− Pixel Sensor array. The timing
and control circuitry sequences through the rows of the
array, resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
analog−to−digital converter (ADC). The output from the
ADC is a 12−bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain). The sensor also offers a high dynamic range
mode of operation where multiple images are combined
on−chip to produce a single image at 16−bit per pixel value.
A compression mode is further offered to allow the 16 bits
per pixel to be transmitted to the host system as a 12−bit
value with close to zero loss in image quality.
www.onsemi.com
3
AR0230CS
Digital
I/O
power!
Digital
Core
power!
HiSPi
PLL
Analog
power! power! power!
Analog
power!
1.5 kΩ@
1.5 kΩ@
V
DD_
SLVS
V
DD_
IO
V
DD
V
DD_
PLL
V
AA
V
AA_
PIX
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_N
SLVS2_P
SLVS3_P
SLVS3_N
SLVSC_P
SLVSC_N
FLASH
SHUTTER
Master clock
(6−48 MHz)
EXTCLK
From
controller
S
ADDR
S
DATA
SCLK
TRIGGER
OE_BAR
RESET_BAR
TEST
D
GND
To
controller
A
GND
Digital
ground
V
DD_
IO
V
DD
V
DD_
SLVS V
DD_
PLL V
AA
V
AA_
PIX
Analog
ground
NOTES:
1. All power supplies must be adequately decoupled
2. ON Semiconductor recommends a resistor value of 1.5kΩ, but a greater value may be used for
slower two−wired speed.
3. The parallel interface output pads can be left unconnected if the serial output interface is used.
4. ON Semiconductor recommends that 0.1
μF
and 10
μF
decoupling capacitors for each power
supply are mounted as close as possible to the pad. Actual values and results may vary
depending on lay out and design considerations. Refer to the AR0230CS demo headboard
schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that
coupling with the digital power planes is minimized.
6. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage
currents.
Figure 2. Typical Configuration: Serial Four−Lane HiSPi Interface
www.onsemi.com
4
AR0230CS
Digital
I/O
power!
Digital
Core
power!
PLL
Analog
power! power!
Analog
power!
1.5 kΩ@
1.5 kΩ@
V
DD_
IO
V
DD
V
DD_
PLL
V
AA
V
AA_
PIX
Master clock
(6−48 MHz)
EXTCLK
D
OUT
[11:0]
S
ADDR
S
DATA
SCLK
TRIGGER
OE_BAR
RESET_BAR
TEST
D
GND
PIXCLK
LINE_VALID
FRAME_VALID
FLASH
SHUTTER
A
GND
To
controller
From
controller
Digital
ground
V
DD_
IO
V
DD
V
DD_
PLL V
AA
V
AA_
PIX
Analog
ground
Figure 3. Typical Configuration: Serial Four−Lane HiSPi Interface
NOTES:
7. All power supplies must be adequately decoupled.
8. ON Semiconductor recommends a resistor value of 1.5kΩ, but a greater value may be used for
slower two−wired speed.
9. The serial interface output pads and V
DD
SLVS can be left unconnected if the parallel output
interface is used.
10. ON Semiconductor recommends that 0.1
μF
and 10
μF
decoupling capacitors for each power
supply are mounted as close as possible to the pad. Actual values and results may vary
depending on lay out and design considerations. Refer to the AR0230CS demo headboard
schematics for circuit recommendations.
11. ON Semiconductor recommends that analog power planes are placed in a manner such that
coupling with the digital power planes is minimized.
12. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage
currents.
13. The EXTCLK input is limited to 6−48 MHz
www.onsemi.com
5
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
