Consider the N8 or S8 Packages for Alternate Source
*Connected internally. Do not connect external circuitry to these pins. Consult LTC Marketing for parts specified with wider operating temperature ranges.
The
q
denotes specifications which apply over the full operating
temperature range otherwise specifications are at T
A
= 25°C. V
IN
= 10V, I
LOAD
= 0, unless otherwise specified.
SYMBOL
V
OUT
PARAMETER
Output Voltage (Note 2)
CONDITIONS
LT1027A
LT1027B, C, D
LT1027E
LT1027A, B
LT1027C
LT1027D
LT1027E
q
q
q
q
ELECTRICAL CHARACTERISTICS
TCV
OUT
Output Voltage Temperature Coefficient
(Note 3)
2
U
U
W
W W
U
W
(Note 1)
Operating Temperature Range
LT1027C ................................................ 0°C to 70°C
LT1027M
(OBSOLETE) ...............
– 55°C to 125°C
Storage Temperature Range
All Devices ....................................... – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
TOP VIEW
8
NC*
NR 1
GND 2
V
TRIM
3
V
OUT
4
TOP VIEW
8
7
6
5
V
IN
NC*
NC*
NC*
7 NC*
6
5
N8 PACKAGE
8-LEAD PDIP
V
OUT
V
TRIM
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 100°C,
θ
JA
= 180°C/W
ORDER PART NUMBER
LT1027CCS8-5
LT1027DCS8-5
LT1027ECS8-5
S8 PART MARKING
1027C5
1027D5
1027E5
MIN
4.9990
4.9975
4.9950
TYP
MAX
UNITS
V
5.000 5.0010
5.000 5.0025
5.000 5.0050
1
2
2
3
2
3
5
7.5
ppm/°C
sn1027 1027fcs
LT1027
The
q
denotes specifications which apply over the full operating
temperature range otherwise specifications are at T
A
= 25°C. V
IN
= 10V, I
LOAD
= 0, unless otherwise specified.
SYMBOL
PARAMETER
Line Regulation (Note 4)
CONDITIONS
8V
≤
V
IN
≤
10V
q
ELECTRICAL CHARACTERISTICS
MIN
TYP
6
3
MAX
12
25
6
8
6
8
120
3.1
3.5
UNITS
ppm/V
ppm/V
ppm/V
ppm/V
ppm/mA
ppm/mA
ppm/mA
mA
mA
mV
µV
P-P
10V
≤
V
IN
≤
40V
q
Load Regulation (Notes 4, 6)
Sourcing Current
0
≤
I
OUT
≤
15mA
Sinking Current
0
≥
I
OUT
≥
– 10mA
q
q
–8
–10
–3
30
2.2
Supply Current
q
V
TRIM
Adjust Range
e
n
Output Noise (Note 5)
Temperature Hysteresis
Long Term Stability
0.1Hz
≤
f
≤
10Hz
10Hz
≤
f
≤
1kHz
H package;
∆T
= 25°C
H package
q
±30
±50
3
2.0
10
20
6.0
µV
RMS
ppm
ppm/month
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of the part may be impaired.
Note 2:
Output voltage is measured immediately after turn-on. Changes
due to chip warm-up are typically less than 0.005%.
Note 3:
Temperature coefficient is determined by the "box" method in
which the maximum
∆V
OUT
over the temperature range is divided by
∆T.
Note 4:
Line and load regulation measurements are done on a pulse basis.
Output voltage changes due to die temperature change must be taken into
account separately. Package thermal resistance is 150°C/W for TO-5 (H),
130°C/W for PDIP (N8), and 180°C/W for plastic SO (SO-8).
Note 5:
RMS noise is measured with an 8-pole bandpass filter with a
center frequency of 30Hz and a Q of 1.5. The filter output is then rectified
and integrated for a fixed time period, resulting in an average, as opposed
to RMS voltage. A correction factor is used to convert average to RMS.
This value is then used to obtain RMS noise voltage in the 10Hz to 1000Hz
frequency band. This test also screens for low frequency "popcorn" noise
within the bandwidth of the filter. Consult factory for 100% 0.1Hz to 10Hz
noise testing.
Note 6:
Devices typically exhibit a slight negative DC output impedance of
– 0.015Ω. This compensates for PC trace resistance, improving regulation
at the load.
TYPICAL PERFOR A CE CHARACTERISTICS
Ripple Rejection
100
120
110
REJECTION (dB)
V
IN
= 10V
OUTPUT IMPEDANCE (Ω)
10
OUTPUT VOLTAGE (V)
100
90
80
70
60
50
10
100
1k
FREQUENCY (Hz)
10k
1027 G01
U W
Output Impedance vs Frequency
100
5.006
∆I
=
±3mA
AC
I
SOURCE
= 5mA
5.004
5.002
5.000
4.998
4.996
0.01
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
1027 G02
Output Voltage
1
0.1
4.994
–50
–25
50
25
0
TEMPERATURE (°C)
75
100
1027 G03
sn1027 1027fcs
3
LT1027
TYPICAL PERFOR A CE CHARACTERISTICS
Start-Up and Turn-Off (No Load)
Start-Up and Turn-Off
2.5
V
OUT
1V/DIV
10V
V
IN
1027 G04
V
OUT
1V/DIV
10V
V
IN
R
L
= 1k, C
L
= 4.7µF
1027 G05
SUPPLY CURRENT (mA)
1µs/DIV
Load Regulation
800
500
CHANGE IN OUTPUT VOLTAGE (µV)
CHANGE IN OUTPUT VOLTAGE (µV)
400
0
–400
–800
–1200
–1600
–10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16
Sink Source
I
OUT
(mA)
1027 G07
300
200
100
0
–100
–200
–300
–400
–500
8
12
16
20 24
28 32
INPUT VOLTAGE (V)
36
40
OUTPUT NOISE DENSITY (nV/√Hz)
Output Settling Time (Sourcing)
V
OUT
400µV/DIV
AC COUPLED
–10mA
LOAD STEP
2µs/DIV
1027 G10
1
0mA
LOAD STEP
2µs/DIV
1027 G11
5µV/DIV
V
OUT
400µV/DIV
AC COUPLED
4
U W
Quiescent Current
2.0
1.5
1.0
500µs/DIV
0.5
0
0
5
10
15 20
25 30
INPUT VOLTAGE (V)
35
40
1027 G06
Line Regulation
200
180
160
140
120
100
80
60
40
20
0
400
Output Noise Voltage Density
C
NR
= 0
C
NR
= 1µF
10
100
1k
FREQUENCY (Hz)
10k
1027 G09
1027 G08
Output Settling Time (Sinking)
0.1Hz to 10Hz Output Noise
Filtering = 1 zero at 0.1Hz
2 poles at 10Hz
1sec/DIV
1027 G12
sn1027 1027fcs
LT1027
APPLICATI
S I FOR ATIO
U
to approximately 1.2µV
RMS
in a 10Hz to 1kHz bandwidth.
Transient response is not affected by this capacitor. Start-
up settling time will increase to several milliseconds due
to the 7kΩ impedance looking into the NR pin. The
capacitor
must
be a low leakage type. Electrolytics are
not
suitable for this application. Just 100nA leakage current
will result in a 150ppm error in output voltage. This pin is
the most sensitive pin on the device. For maximum protec-
tion a guard ring is recommended. The ring should be
driven from a resistive divider from V
OUT
set to 4.4V (the
open-circuit voltage on the NR pin).
Transient Response
The LT1027 has been optimized for transient response.
Settling time is under 2µs when an AC-coupled 10mA load
transient is applied to the output. The LT1027 achieves
fast settling by using a class B NPN/PNP output stage.
When sinking current, the device may oscillate with ca-
pacitive loads greater than 100pF. The LT1027 is stable
with all capacitive loads when at no DC load or when
sourcing current, although for best settling time either no
output bypass capactor or a 4.7µF tantalum unit is recom-
mended. An 0.1µF ceramic output capacitor will
maximize
output ringing
and is
not
recommended.
Kelvin Connections
Although the LT1027 does not have true force-sense
capability, proper hook-up can improve line loss and
ground loop problems significantly. Since the ground pin
of the LT1027 carries only 2mA, it can be used as a low-
side sense line, greatly reducing ground loop problems on
the low side of the reference. The V
OUT
pin should be close
to the load or connected via a heavy trace as the resistance
of this trace directly affects load regulation. It is important
to remember that a 1.22mV drop due to trace resistance is
equivalent to a 1LSB error in a 5V
FS
, 12-bit system.
The circuits in Figures 2 and 3 illustrate proper hook-up to
minimize errors due to ground loops and line losses.
Losses in the output lead can be further reduced by adding
a PNP boost transistor if load current is 5mA or higher. R2
can be added to further reduce current in the output sense
load.
sn1027 1027fcs
Effect of Reference Drift on System Accuracy
A large portion of the temperature drift error budget in
many systems is the system reference voltage. Figure 1
indicates the maximum temperature coefficient allowable
if the reference is to contribute no more than 0.5LSB error
to the overall system performance. The example shown is
a 12-bit system designed to operate over a temperature
range from 25°C to 65°C. Assuming the system calibra-
tion is performed at 25°C, the temperature span is 40°C.
It can be seen from the graph that the temperature coeffi-
cient of the reference must be no worse than 3ppm/°C if
it is to contribute less than 0.5LSB error. For this reason,
the LT1027 has been optimized for low drift.
MAXIMUM TEMPERATURE COEFFICIENT FOR
0.5LSB ERROR (ppm/°C)
100
8-BIT
10-BIT
10
12-BIT
14-BIT
1.0
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE SPAN (°C)
1027 AI01
Figure 1. Maximum Allowable Reference Drift
Trimming Output Voltage
The LT1027 has an adjustment pin for trimming output
voltage. The impedance of the V
ADJ
pin is about 20kΩ with
an open-circuit voltage of 2.5V. A
±30mV
guaranteed trim
range is achievable by tying the V
ADJ
pin to the wiper of a
10k potentiometer connecting between the output and
ground. Trimming output voltage does not affect the TC of
the device.
Noise Reduction
The positive input of the internal scaling amplifier is
brought out as the Noise Reduction (NR) pin. Connecting
a 1µF Mylar capacitor between this pin and ground will
reduce the wideband noise of the LT1027 from 2.0µV
stm32/stm8
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