DATASHEET
HS-26CLV31RH, HS-26CLV31EH
Radiation Hardened 3.3V Quad Differential Line Drivers
The Intersil HS-26CLV31RH, HS-26CLV31EH are radiation
hardened 3.3V quad differential line drivers designed for
digital data transmission over balanced lines, in low voltage,
RS-422 protocol applications. CMOS processing assures low
power consumption, high speed, and reliable operation in the
most severe radiation environments.
The HS-26CLV31RH, HS-26CLV31EH accept CMOS level inputs
and converts them to differential outputs. Enable pins allow
several devices to be connected to the same data source and
addressed independently. These devices have unique outputs that
become high impedance when the driver is disabled or
powered-down, maintaining signal integrity in multi-driver
applications.
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD
5962-96663.
A “hot-link” is also provided on
our homepage for downloading.
FN4898
Rev 4.00
May 23, 2013
Features
• Electrically screened to SMD #
5962-96663
• QML qualified per MIL-PRF-38535 requirements
• 1.2 micron radiation hardened CMOS
- Total dose . . . . . . . . . . . . . . . . . . . . . . . . 300 krad (Si) (max)
- Single event upset LET . . . . . . . . . . . . . 100MeV/mg/cm
2
)
- Single event latch-up immune
• Extremely low stand-by current . . . . . . . . . . . . . 100µA (max)
• Operating supply range . . . . . . . . . . . . . . . . . . . . . 3.0V to 3.6V
• CMOS level inputs . . . . . . .V
IH
> (0.7) (V
DD
); V
IL
< (0.3) (V
DD
)
• Differential outputs . . . . . . . . . . . . . . . V
OH
> 1.8V; V
OL
< 0.5V
• High impedance outputs when disabled or powered down
• Low output impedance . . . . . . . . . . . . . . . . . . . . . .10 or less
• Full -55°C to +125°C military temperature range
• Pb-Free (RoHS Compliant)
Applications
• Line transmitter for MIL-STD-1553 serial data bus
Ordering Information
ORDERING NUMBER
(Note 1)
5962F9666302QEC
5962F9666302QXC
5962F9666302VEC
5962F9666302VXC
5962F9666302V9A
HS1-26CLV31RH/PROTO
HS9-26CLV31RH/PROTO
5962F9666304VEC
5962F9666304VXC
5962F9666304V9A
HS0-26CLV31RH/SAMPLE
5962F9666302VYC
HS9G-26CLV31RH/PROTO
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. The lid of these packages are connected to the ground pin of the device.
INTERNAL
MKT. NUMBER
HS1-26CLV31RH-8
HS9-26CLV31RH-8
HS1-26CLV31RH-Q
HS9-26CLV31RH-Q
HS0-26CLV31RH-Q
HS1-26CLV31RH/PROTO
HS9-26CLV31RH/PROTO
HS1-26CLV31EH-Q
HS9-26CLV31EH-Q
HS0-26CLV31EH-Q
HS0-26CLV31RH/SAMPLE
HS9G-26CLV31RH-Q (Note 2)
HS9G-26CLV31RH/PROTO (Note 2)
Q 5962F96 66302VYC
HS9G-26CLV31RH/PROTO
HS1-26CLV31RH/PROTO
HS9-26CLV31RH/PROTO
Q 5962F96 66304VEC
Q 5962F96 66304VXC
PART
MARKING
Q 5962F96 66302QEC
Q 5962F96 66302QXC
Q 5962F96 66302VEC
Q 5962F96 66302VXC
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
(RoHS Compliant)
16 Ld SBDIP
16 Ld FLATPACK
16 Ld SBDIP
16 Ld FLATPACK
Die
16 Ld SBDIP
16 Ld FLATPACK
16 Ld SBDIP
16 Ld FLATPACK
Die
Die
16 Ld FLATPACK
16 Ld FLATPACK
K16.A
K16.A
D16.3
K16.A
D16.3
K16.A
PKG.
DWG. #
D16.3
K16.A
D16.3
K16.A
FN4898 Rev 4.00
May 23, 2013
Page 1 of 3
HS-26CLV31RH, HS-26CLV31EH
Pin Configurations
HS1-26CLV31RH, HS1-26CLV31EH
(16 LD SBDIP)
CDIP2-T16
TOP VIEW
AIN 1
AO 2
AO 3
ENABLE 4
BO 5
BO 6
BIN 7
GND 8
16 VDD
15 DIN
14 DO
13 DO
12 ENABLE
11 CO
10 CO
9 CIN
AIN
AO
AO
ENABLE
BO
BO
BIN
GND
HS9-26CLV31RH, HS9-26CLV31EH
(16 LD FLATPACK)
CDFP4-F16
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
DIN
DO
DO
ENABLE
CO
CO
CIN
Logic Diagram
ENABLE
ENABLE
DIN
CIN
BIN
AIN
DO DO
CO CO
BO BO
AO AO
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
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For information regarding Intersil Corporation and its products, see
www.intersil.com
FN4898 Rev 4.00
May 23, 2013
Page 2 of 3
HS-26CLV31RH, HS-26CLV31EH
Die Characteristics
DIE DIMENSIONS:
96.5 mil x 195 mils x 21 mils
(2450 x 4950)
Substrate:
AVLSI1RA
Backside Finish:
Silicon
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorus Silicon Glass)
Thickness: 8k
Å
±1k
Å
Metallization:
Bottom: Mo/TiW
Thickness: 5800
Å
±
1kÅ
Top: AlSiCu (Top)
Thickness: 10k
Å
±1k
Å
ASSEMBLY RELATED INFORMATION:
Substrate Potential (Powered Up):
V
DD
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Bond Pad Size:
110µm x 100µm
Metallization Mask Layout
HS-26CLV31RH, HS-26CLV31EH
TABLE 1. HS-26CLV31RH, HS-26CLV31EH PAD COORDINATES
(16) VDD
(16) VDD
(15) DIN
(1) AIN
RELATIVE TO PIN 1
PIN
NUMBER
1
PAD
NAME
AIN
A0
A0
ENABLE
B0
B0
BIN
GND
GND
CIN
C0
C0
ENABLE
D0
D0
DIN
VIN
VIN
X COORDINATES Y COORDINATES
0
0
0
0
0
0
0
852.4
1062.4
1912.8
1912.8
1912.8
1912.8
1912.8
1912.8
1912.8
1062.4
852.4
0
-570.7
-1483.5
-2124.8
-2873.5
-3786.3
-4357
-4357
-4357
-4357
-3786.3
-2873.5
-2124.8
-1483.5
-570.7
0
0
0
AO (2)
(14) DO
2
3
4
5
AO (3)
(13) DO
6
7
8
8
ENABLE (4)
(12) ENABLE
9
10
11
BO (5)
(11) CO
12
13
14
15
BO (6)
(10) CO
16
16
NOTE: Dimensions in microns
GND (8)
GND (8)
CIN (9)
BIN (7)
FN4898 Rev 4.00
May 23, 2013
Page 3 of 3