SID1102K
SCALE-iDriver
Family
Up to 5 A Single Channel IGBT/MOSFET Gate Driver Providing
Reinforced Galvanic Isolation up to 1200 V Blocking Voltage
Product Highlights
Highly Integrated, Compact Footprint
•
Single channel providing up to 5 A peak gate drive current
•
Auxiliary outputs for external booster stage for increased peak drive
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Description
The SID1102K is a single channel IGBT and MOSFET gate driver in an
eSOP package. Reinforced galvanic isolation is provided by Power
Integrations’ revolutionary solid insulator FluxLink technology. Up to
5 A peak output drive current enables the product to drive devices with
nominal currents of up to 300 A. For gate drive requirements that
exceed the stand-alone capability of SID1102K, additionally AUXGL and
AUXGH output pins can drive external n-channel MOSFETs as a booster
stage, giving customers full freedom and control of their system
design.
Controller (PWM) signals are compatible with 5 V CMOS logic, which
may also be adjusted to 15 V levels by using external resistor divider.
current
Integrated FluxLink™ technology providing safe isolation between
primary-side and secondary-side
Rail-to-rail stabilized output voltage
Unipolar supply voltage for secondary-side
Suitable for 600 V / 650 V / 1200 V IGBT and MOSFET switches
Up to 75 kHz switching frequency
Propagation delay jitter ±5 ns
-40 °C to 125 °C operating ambient temperature
High common-mode transient immunity
eSOP package with 9.5 mm creepage and clearance
Product Portfolio
Product
1
SID1102K
Table 1. SCALE-iDriver Portfolio.
Notes:
1. Package: eSOP-R16B.
Protection / Safety Features
(UVLO)
•
Undervoltage lock-out protection for primary and secondary-side
Peak Output Drive Current
5 A without external booster
Full Safety and Regulatory Compliance
•
100% production partial discharge test
•
100% production HIPOT compliance testing at 6 kV RMS 1 s
•
Reinforced insulation meets VDE V 0884-10
Green Package
Applications
•
Halogen free and RoHS compliant
•
General purpose and servo drives
•
UPS, solar, welding inverters and power supplies
Figure 2.
eSOP-R16B Package.
SCALE-iDriver
VGXX
Primary-Side
Logic
Secondary-Side
Logic
VISO
IN
AUXGH
*
V
IN
V
VCC
+
-
VCC
G
FluxLink
AUXGL
GND
VEE
V
TOT
+
-
COM
*Optional for gate peak current requirements >5 A
PI-8527-111317
Figure 1.
Typical Application Schematic with External n-Channel MOSFET Booster Stage.
www.power.com
May 2018
This Product is Covered by Patents and/or Pending Patent Applications.
SID1102K
VGXX
BOOTSTRAP
CHARGE PUMP
VISO
LEVEL
SHIFTER
AUXGH
FluxLink
TRANSMITTER
RECEIVER
G
AUXGL
VCC
GND
IN
CORE LOGIC
SUPPLY
MONITORING
AUXILIARY
POWER SUPPLIES
CORE LOGIC
SUPPLY
MONITORING
AUXILIARY
POWER SUPPLIES
VISO
VEE CONTROL
COM
VEE
PI-8539-111317
Figure 3.
Functional Block Diagram.
Pin Functional Description
VCC Pin (Pin 1)
This pin is the primary-side supply voltage connection.
GND Pin (Pin 3-6)
This pin is the connection for the primary-side ground potential.
All primary-side voltages refer to the pin.
IN Pin (Pin 7)
This pin is the input for the logic command signal.
NC Pins (Pin 8, Pin 9)
These pins must be un-connected. Minimum PCB pad size for
soldering is required.
VEE Pin (Pin 10)
Common (IGBT emitter/MOSFET source) output supply voltage.
AUXGH Pin (Pin 11)
This pin is the high side driver signal for external n-channel MOSFET
booster stage.
VGXX Pin (Pin 12)
This pin is the bootstrap and charge pump supply voltage source.
G Pin (Pin 13)
This pin is the driver output (turn-on/turn-off) connection.
VISO Pin (Pin 14)
This pin is the input for the secondary-side positive supply voltage.
COM Pin (Pin 15)
This pin provides the secondary-side reference potential.
AUXGL Pin (Pin 16)
This pin is the low side driver signal for external n-channel MOSFET
booster stage.
Figure 4.
Pin Configuration.
VCC 1
GND 3-6
IN 7
NC 8
16 AUXGL
15 COM
14 VISO
13 G
12 VGXX
11 AUXGH
10 VEE
9 NC
PI-8540-110717
SCALE-iDriver Functional Description
The single channel SCALE-iDriver™ SID1102K drives IGBTs and
MOSFETs or other semiconductor power switches with a blocking
voltage of up to 1200 V and provides reinforced isolation between
micro-controller and the power semiconductor switch.
Command signals are transferred from the primary (IN) to
secondary-side via FluxLink isolation technology. The G pin supplies
a positive gate voltage and charges the semiconductor gate during
the turn-on process. During the turn-off process the G pin supplies
the negative voltage and discharges the gate.
2
Rev. D 05/18
www.power.com
SID1102K
Additionally, dedicated AUXGL and AUXGH output pins are available to
drive external n-channel MOSFETs as booster stage that can be
configured to provide increased peak output gate drive current.
Power Supplies
The SID1102K requires two power supplies. One for the primary-side
(V
VCC
), which powers the primary-side logic and communication with
the secondary (insulated) side. The other supply voltage (V
TOT
) is
required for the secondary-side. V
TOT
is applied between VISO pin
and COM pin. V
TOT
should be insulated from the primary-side and
should provide at least the same insulation capabilities as the
SCALE-iDriver. V
TOT
should have a low capacitive coupling to the
primary or any other secondary-side. The positive gate-emitter
source voltage is provided by V
VISO
, which is internally generated and
stabilized to 15 V (typically) with respect to VEE. The negative
gate-emitter source voltage is provided by VEE with respect to COM.
Due to the limited current sourcing/sinking capabilities of the VEE pin,
any additional load needs to be applied between the VISO and COM
pins. No additional load between VISO and VEE pins or between VEE
and COM pins is allowed.
Input (Primary-Side)
The input (IN) logic is designed to work directly with micro-control-
lers using 5 V CMOS logic. If the physical distance between the
controller and the SCALE-iDriver is large or if a different logic level is
required, the resistive divider in Figure 6 is recommended. This
solution adjusts the logic level as necessary and will also improve the
driver’s noise immunity.
Gate driver commands are transferred from the IN pin to the G pin
with a propagation delay t
P(LH)
and t
P(HL)
.
Output (Secondary-Side)
The gate of the power semiconductor switch should be connected to
the SCALE-iDriver output via pin G, using suitable gate resistor R
G
as
shown in Figure 7.
Note that most power semiconductor data sheets specify an internal
gate resistor R
GINT
, which is already integrated into power semicon-
ductor switch. In addition to R
GINT
, external resistor device R
G
is
specified to set-up the gate current level to the application require-
ments. Careful consideration should be given to the power dissipa-
tion and peak current associated with the external gate resistor.
The G pin output current source (I
G(H)
, I
G(L)
) of SID1102K is capable of
sinking and sourcing (typically) 5 A at 25 °C. The SCALE-iDriver’s
internal resistances are described as R
GHI
and R
GLI
respectively. If the
gate resistor attempts to draw a higher peak current, the peak
current will be internally limited to a safe value.
Safe Power-Up and Power-Down
It is recommended during power-up and power-down that the IN pin
stays at logic low. Any supply voltage related to VCC, VISO, VEE and
VGXX pins should be stabilized using ceramic capacitors C
1
, C
2
, C
S1
,
C
S2
, and C
GXX
respectively as shown in Figure 5 and Figure 7. After
supply voltages reach their nominal values, the driver will begin to
function after a time delay t
START
.
Short-Pulse Operation
If command signals applied to the IN pin are shorter than the
minimum specified by t
GE(MIN)
, then SID1102K output signals at G,
AUXGH, and AUXGL pins will extend to value t
GE(MIN)
. The duration of
pulses longer than t
GE(MIN)
will not be changed.
Figure 6.
SCALE-iDriver
IN
VCC
C
1
C
2
GND
PI-8532-110917
Figure 5.
Recommended Circuitry for Standard 5 V IN Logic Level.
SCALE-iDriver
R
1
R
2
IN
VCC
C
1
C
2
GND
PI-8533-110917
Recommended Circuitry for Increased IN Logic Levels.
For R
1
= 3.3 kΩ and R
2
= 1 kΩ the IN Logic Level is 15 V.
SCALE-iDriver
VGXX
VISO
C
S1
AUXGH
C
GXX
D
STO
R
G
G
AUXGL
V
TOT
+
-
R
3
VEE
C
S2
COM
PI-8534-110917
Figure 7.
SID1102K without External Booster Stage.
3
www.power.com
Rev. D 05/18
SID1102K
Application Example and Components Selection
Without Booster
Figure 5 and Figure 7 show the primary-side and secondary-side
schematic and typical components used for SID1102K design without
a booster stage, in which the primary-side supply voltage (V
VCC
) will
be connected between VCC and GND pins and supported through
supply bypass ceramic capacitors C
1
(4.7
µF
typically) and C
2
(470 nF
typically). If the command signal voltage level is higher than the
rated IN pin voltage, a resistive voltage divider should be used
(Figure 6). Additional capacitor C
F
can be used to provide input signal
filtering as shown in Figure 8. The filter time
τ
can be calculated
according to equation (1):
Application Example and Components Selection
With Booster
The primary-side can be setup identical as described in the previous
section refering to Figure 5 or Figure 6 or Figure 8.
The secondary-side is slightly extended by the booster MOSFETs T
1
and T
2
(BSO220N03MD G for example) and the addition of discrete
gate resistors R
GON
and R
GOFF
as well as diode D
2
(PMEG4010CEJ for
example). All other components can be kept, values might be
adapted to the relevant target power semiconductor switching device,
such as gate resistors and the supply bypass capacitors C
S1
, C
S2
.
SCALE-iDriver
R
#
R
τ
=
R
1
+
R
2
#
C
F
1
2
SCALE-iDriver
(1)
VGXX
VISO
C
S1
AUXGH
C
GXX
T
1
D
STO
R
G
R
GON
R
GOFF
D
2
R
3
G
R
1
IN
AUXGL
V
TOT
+
-
T
2
VCC
VEE
R
2
C
F
C
1
C
2
GND
C
S2
COM
PI-8535-110917
Figure 9.
SID1102K with External Boosterstage.
PI-8536-110917
Figure 8.
Optional Input Signal Filtering.
The secondary-side isolated power supply (V
TOT
) is connected
between VISO and COM. The positive voltage rail (V
VISO
) is supported
through ceramic capacitor C
S1
. The negative voltage rail (V
VEE
) is simi-
larly supported through capacitor C
S2
. Typically, C
S1
and C
S2
should be
at least 3
µF
multiplied by the total gate charge of the power
semiconductor switch (Q
GATE
) divided by 1
µC.
A 10 nF capacitor C
GXX
is connected between the G and VGXX pins.
To ensure gate voltage stabilization and collector current limitation
during short-circuit the gate is connected to V
VISO
through Schottky
diode D
STO
.
To avoid parasitic power-switch-conduction during system power-on
the gate is connected to COM through 22 kΩ resistor R
3
as shown in
Figure 7.
Gate resistors are located physically close to the power semiconduc-
tor switch. As these components can get hot, it is recommended that
they are placed away from the SCALE-iDriver.
In Off-state (VIN = 0 V) the AUXGL pin provides a positive voltage to
the gate terminal of T
2
with reference to the MOSFETs source
potential e.g. COM. T
2
conducts the semiconductors gate terminal to
COM via R
GOFF
, providing a negative voltage with reference to VEE to
the semiconductors gate (IGBT in this case). The power semiconduc-
tor device is off.
When VIN changes from 0 V to 5 V, T
2
is turned off by applying 0 V
to the AUXGL pin with reference to COM. At the same time T
1
is
turned on by providing a positive gate voltage via AUXGH to the gate
of T
1
with reference to G. Since the G pin is connected to V
TOT
in
On-state, the potential of the AUXGH pin needs to be higher than
V
TOT
. This is achieved via SCALE-iDriver’s internal charge pump /
bootstrap. When T
1
conducts, it provides a positive gate voltage to
the power semiconductors gate with reference to VEE. The power
semiconductor device is on.
When VIN changes from 5 V to 0 V, it has to be considered, that R
GON
and R
GOFF
are paralleled, consequently resulting in a R
GOFF
< R
GON
for all
chosen. R
G
is placed in series to R
GON
to allow R
GOFF
> R
GON
.
To ensure that no parasitic turn-on of the power semiconductor
switching device occurs when used on the high-side of a half-bridge
topology and under worst case switching conditions, the use of the
Schottky diode D
2
(PMEG4010CEJ for example) is recommended.
Since the current capability of the VGXX pin is limited, it is recom-
mended to restrict the applicable external N-Channel Booster
MOSFETs to those with a gate charge Q
G
≤ 9 nC for T
1
and
Q
G
≤ 5 nC for T
2
.
4
Rev. D 05/18
www.power.com
SID1102K
SCALE-iDriver
VGXX
Primary-Side
Logic
Secondary-Side
Logic
R
1
Command
3.3 kΩ
Signal
VISO
IN
AUXGH
C
S1
4.7
µF
C
GXX
10 nF
D
STO
R
G
VCC
R
2
1 kΩ
C
1
4.7
µF
C
F
VCC
G
C
2
470 nF
GND
FluxLink
AUXGL
GND
V
TOT
+
-
R
3
22 kΩ
VEE
COM
C
S2
4.7
µF
PI-8537-111317
Figure 10. Exemplary Schematic without Booster.
SCALE-iDriver
VGXX
Primary-Side
Logic
Secondary-Side
Logic
R
1
Command
3.3 kΩ
Signal
C
GXX
C
S1
4.7
µF
10 nF
VISO
T
1
R
G
20
Ω
V
TOT
+
-
T
2
D
STO
R
GON
R
GOFF
D
2
R
3
22 kΩ
IN
AUXGH
VCC
R
2
1 kΩ
C
1
4.7
µF
C
F
VCC
G
C
2
470 nF
GND
FluxLink
AUXGL
GND
VEE
COM
C
S2
4.7
µF
PI-8538-111317
Figure 11. Exemplary Schematic with Booster.
5
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Rev. D 05/18
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