AS4C32M16MD1A-5BCN
1. GENERAL DESCRIPTION
This
AS4C32M16MD1A-5BCN
is 536,870,912 bits synchronous double data rate Dynamic RAM. Each 134,217,728 bits bank is
organized as 8,192 rows by 1024 columns by 16 bits fabricated with
Alliance Memory’s
high performance CMOS technology. This
device uses a double data rate architecture to achieve high- speed operation. The double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Range of operating
frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high
bandwidth and high performance memory system applications.
2.
FEATURES
•
VDD/VDDQ = 1.7~1.95V
•Data
width: x16
•Clock
rate: 200MHz
•Partial
Array Self-Refresh(PASR)
•Auto
Temperature Compensated Self-Refresh(ATCSR)
•Power
Down Mode
•Deep
Power Down Mode (DPD Mode)
•Programmable
output buffer driver strength
•Four
internal banks for concurrent operation
•Data
mask (DM) for write data
•Clock
Stop capability during idle periods
•Auto
Pre-charge option for each burst access
•Double
data rate for data output
CAS Latency: 2 and 3
Burst Length: 2, 4, 8 and 16
Burst Type: Sequential or Interleave
64 ms Refresh period
Interface: LVCMOS
Operating Temperature Range
Extended (-30°C to +85°C)
•Differential
clock inputs (CK and
CK )
•
Bidirectional, data strobe (DQS)
•
PKG Type
x16 : 8.0 x 9.0mm 60 Ball FPBGA
(Fine Pitch Ball Grid Array)
Table 1. Speed Grade Information
Speed Grade
Clock Frequency
CAS Latency
t
RCD
(ns)
15
t
RP
(ns)
15
DDR1-400
200MHz
3
Table 2. Ordering Information
Product part No
Org
Temperature
Extended
-30°C
to
+85°C
Max Clock (MHz)
200
Package
60-ball
FPBGA
AS4C32M16MD1A-5BCN
32Mx 16
Confidential
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Rev.1.2 July 2016
AS4C32M16MD1A-5BCN
3.1 Signal Descriptions
Table
3
— Signal Descriptions
SIGNAL NAME
CK,/CK
TYPE
DESCRIPTION
CKE
CS
RAS/CAS/WE
DM,
LDM, UDM
Clock: CK and CK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK
Input
and negative edge of CK. Input and output data is referenced to the
crossing of CK and CK (both directions of crossing). Internal clock
signals are derived from CK/CK.
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal
clock signals, and device input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in
Input
any bank). CKE is synchronous for all functions except for SELF
REFRESH EXIT, which is achieved asynchronously. Input buffers,
excluding CK, CK and CKE, are disabled during power-down and self
refresh mode which are contrived for low standby power consumption.
Chip Select: CS enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS is
Input
registered HIGH. CS provides for external bank selection on systems
with multiple banks. CS is considered part of the command code.
Input Command Inputs: RAS, CAS and WE (along with CS) define the
command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a
WRITE access. DM is sampled on both edges of DQS. Although DM
Input
pins are input-only, the DM loading matches the DQ and DQS loading.
LDM corresponds to the data on DQ0-DQ7, UDM corresponds to the
data on DQ8-DQ15.
Input
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
Address Inputs: provide the row address for ACTIVE commands, and
the column address and AUTO PRECHARGE bit for READ / WRITE
commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the opcode during a
MODE REGISTER SET command.
Data Bus: Input / Output
BA0,BA1
A [n : 0]
DQ0-DQ15
I/O
LDQS,UDQS
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered with write data. Used to capture write data.
LDQS corresponds to the data on DQ0-DQ7, UDQS corresponds to
the data on DQ8-DQ15.
No Connect: No internal electrical connection is presen
NC
VDDQ
-
Supply
I/O Power Supply
Supply
I/O Ground
Supply
Power Supply
Supply
Ground
VSSQ
VDD
VSS
Confidential
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Rev.1.2 July 2016
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