74LV74
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 4 — 9 December 2015
Product data sheet
1. General description
The 74LV74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD)
inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ
outputs.
The set and reset are asynchronous active LOW inputs that operate independently of the
clock input. Information on the data input is transferred to the nQ output on the
LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action
in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
2. Features and benefits
Wide supply voltage range from 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Direct interface with TTL levels (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Temperature range
74LV74D
74LV74DB
74LV74PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO14
SSOP14
Description
plastic shrink small outline package; 14 leads; body width
5.3 mm
Version
SOT337-1
SOT402-1
Type number Package
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
Nexperia
74LV74
Dual D-type flip-flop with set and reset; positive-edge trigger
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Functional diagram
74LV74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 9 December 2015
2 of 18
Nexperia
74LV74
Dual D-type flip-flop with set and reset; positive-edge trigger
Fig 4.
Logic diagram (one flip-flop)
74LV74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 9 December 2015
3 of 18
Nexperia
74LV74
Dual D-type flip-flop with set and reset; positive-edge trigger
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration SO16 and (T)SSOP16
5.2 Pin description
Table 2.
Symbol
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
asynchronous reset-direct input (active-LOW)
data inputs
clock input (LOW-to-HIGH), edge-triggered)
asynchronous set-direct input (active-LOW)
true flip-flop outputs
complement flip-flop outputs
ground (0 V)
complement flip-flop outputs
true flip-flop outputs
asynchronous set-direct input (active-LOW)
clock input (LOW-to-HIGH), edge-triggered)
data inputs
asynchronous reset-direct input (active-LOW)
supply voltage
74LV74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 9 December 2015
4 of 18
Nexperia
74LV74
Dual D-type flip-flop with set and reset; positive-edge trigger
6. Functional description
Table 3.
Input
nSD
L
H
L
H
H
[1]
Function table
[1]
Output
nRD
H
L
L
H
H
nCP
X
X
X
nD
X
X
X
L
H
nQ
H
L
H
-
-
nQ
L
H
H
-
-
Q
n+1
-
-
-
L
H
nQ
n+1
-
-
-
H
L
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH clock transition;
Q
n+1
= state after the next LOW-to-HIGH CP transition
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
I
IK
V
I
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO16 package
(T)SSOP16 package
[1]
[2]
[3]
[2]
[3]
Conditions
[1]
Min
0.5
-
[1]
Max
+7
20
+7
50
25
50
50
+150
500
400
Unit
V
mA
V
mA
mA
mA
mA
C
mW
mW
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
> V
CC
or V
O
< 0
0.5
V < V
O
< V
CC
+ 0.5 V
0.5
-
-
-
-
65
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
C.
P
tot
derates linearly with 5.5 mW/K above 60
C.
74LV74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 9 December 2015
5 of 18
国产芯片交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
