Si5348 Rev E Data Sheet
Network Synchronizer for SyncE/ 1588 PTP Telecom Boundary
(T-BC) and Slave (T-SC) Clocks
The Si5348 combines the industry’s smallest footprint and lowest power network syn-
chronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The
Si5348 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless
communications systems, and data center switches requiring both traditional and packet
based network synchronization.
The three independent DSPLLs
™
are individually configurable as a SyncE PLL, IEEE
1588 DCO or a general-purpose PLL for processor/FPGA clocking. The Si5348 can also
be used in legacy SETS systems needing Stratum 3/3E compliance. The optional digital-
ly controlled oscillator (DCO) mode provides precise timing adjustment to 1 ppt for 1588
(PTP) clock steering applications. The unique design of the Si5348 allows the TCXO/
OCXO reference input to determine the device’s frequency accuracy and stability. The
Si5348 is programmable via a serial interface with in-circuit programmable non-volatile
memory so it always powers up into a known configuration. Programming the Si5348 is
easy with
ClockBuilder Pro
™
software. Factory pre-programmed devices are also availa-
ble.
Applications:
• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2
• Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813 network synchronization
48-54 MHz XTAL
XA
TCXO/
OCXO
REF
REFb
IN3
IN4
IN0
IN1
IN2
÷FRAC
÷FRAC
÷FRAC
DSPLL A
Status Flags
I2C / SPI
Status Monitor
Control
NVM
DSPLL C
DSPLL D
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OSC
XB
KEY FEATURES
• Three independent DSPLLs in a single
monolithic IC supporting flexible SyncE/
IEEE 1588 and SETS architectures
• Ultra-low jitter of 95 fs
• Enhanced hitless switching minimizes
output phase transients
• Input frequency range:
• External crystal: 48 to 54 MHz
• REF clock: 5 to 250 MHz
• Diff clock: 8 kHz to 750 MHz
• LVCMOS clock: 8 kHz to 250 MHz
• Output frequency range:
• Differential: 1 PPS to 718.5 MHz
• LVCMOS: 1 PPS to 250 MHz
• Meets the requirements of:
• ITU-T G.8262 (SyncE) EEC Options 1
and 2
• ITU-T G.812 Type III, IV
• ITU-T G.813 Option 1
• Telcordia GR-1244, GR-253
(Stratum-3/3E)
Si5348
silabs.com
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.95
Si5348 Rev E Data Sheet
Feature List
1. Feature List
The Si5348 features are listed below:
• Three independent DSPLLs in a single monolithic IC support-
ing flexible SyncE/IEEE 1588 and SETS architectures
• Ultra-Low Jitter
• 95 fs typ (12 kHz to 20 MHz)
• Meets the requirements of:
• ITU-T G.8273.2 T-BC
• ITU-T G.8262 (SyncE) EEC Options 1 & 2
• ITU-T G.812 Type III, IV
• ITU-T G.813 Option 1
• Telcordia GR-1244, GR-253 (Stratum-3/3E)
• Each DSPLL generates any output frequency from any input
frequency
• Input frequency range:
• External crystal: 48–54 MHz
• REF clock: 5–250 MHz
• Diff clock: 8 kHz–750 MHz
• LVCMOS clock: 8 kHz–250 MHz
• Output frequency range:
• Differential: 1 PPS to 718.5 MHz
• LVCMOS: 1 PPS to 250 MHz
• Independent Frequency-on-the-fly for each DSPLL
• Enhanced hitless switching minimizes output phase transi-
ents for 8 kHz, 19.44 MHz, 25 MHz, and other input frequen-
cies.
• Pin or software controllable DCO on each DSPLL with typical
resolution to 1 ppt/step
• TCXO/OCXO reference input determines DSPLL free-run/hold-
over accuracy and stability
• Programmable jitter attenuation bandwidth per DSPLL: 0.001
Hz to 4 kHz
• Highly configurable output drivers: LVDS, LVPECL, LVCMOS,
HCSL, CML
• Core voltage:
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V
• Built-in power supply filtering
• Status monitoring: LOS, OOF, LOL
• Serial Interface: I
2
C or SPI (3-wire or 4-wire)
• ClockBuilder
TM
Pro software tool simplifies device configura-
tion
• 5 input, 7 output, 64 QFN
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
silabs.com
| Building a more connected world.
Preliminary Rev. 0.95 | 2
Si5348 Rev E Data Sheet
Related Documents
2. Related Documents
Table 2.1. Related Documentation and Software
Document/Resource
Si5348 Rev E Family Reference Manual
Description/URL
To be used in conjunction with this data sheet, which contains more de-
tailed explanations about the operation of the device.
https://www.silabs.com/documents/public/reference-manuals/si534x-8x-rec-
ommended-crystals-rm.pdf
Instructions about how to use the evaluation kits.
TBD
http://www.silabs.com/quality
https://www.silabs.com/products/development-tools/timing/clock#highper-
formance
https://www.silabs.com/products/development-tools/software/clockbuilder-
pro-software
Crystal Reference Manual
Si5348 EVB User Guide
Frequently Asked Questions
Quality and Reliability
Development Kits
ClockBuilder Pro (CBPro) Software
AN1077: Selecting the Right Clocks for Timing Synchro-
https://www.silabs.com/documents/public/application-notes/an1077-select-
nization Applications
ing-clocks-for-timing-synchronization.pdf
UG123: SiOCXO1-EVB Evaluation Board Users Guide
https://www.silabs.com/documents/public/user-guides/UG123.pdf
UGTBD: SiTCXO1-EVB Evaluation Board User's Guide Link TBD
ANTBDX: Holdover Consideration for Si5348 Network
Synchronizer
Link TBD
silabs.com
| Building a more connected world.
Preliminary Rev. 0.95 | 3
Si5348 Rev E Data Sheet
Ordering Guide
3. Ordering Guide
Table 3.1. Si5348 Ordering Guide
# of
DSPLLs
3
—
—
Output Clock Frequency
Range
1 Hz to 718.5 MHz
1 Hz to 350 MHz
—
12.800 MHz
Temperature
Range
–40 to 85 °C
—
—
Ordering Part Number
Si5348A-E-GM
1, 2
Si5348B-E-GM
Si5348-E-EVB
SiOCXO1-EVB
1, 2
Package
RoHS-6, Pb-Free
64-Lead 9x9 QFN
Evaluation Board
OCXO Evaluation
Board
Yes
—
—
Note:
1. Add an R at the end of the device part number to denote tape and reel ordering options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the ClockBuilder Pro software.
Part number format is: Si5348A-Dxxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed
configuration.
Si534fg-Rxxxxx-GM
Timing product family
f =
Packet Network Synchronizer for SyncE/1588 (8)
g = Device
grade
(A, B)
Product
Revision*
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (QFN, -40 °C to +85°C)
*See Ordering Guide table for current product revision
** 5 digits; assigned by ClockBuilder Pro
Figure 3.1. Ordering Part Number Fields
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Preliminary Rev. 0.95 | 4
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Standards Compliance .
4.2 Frequency Configuration
4.3 DSPLL Loop Bandwidth .
4.3.1 Fastlock Feature . .
4.4 Modes of Operation . .
4.4.1 Initialization and Reset
4.4.2 Free-run Mode . .
4.4.3 Lock Acquisition Mode
4.4.4 Locked Mode . . .
4.4.5 Holdover Mode . .
4.4.6 Frequency on the Fly
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. 7
. 7
. 7
. 8
. 8
. 8
. 8
. 9
. 9
. 9
.10
.10
.10
.11
.12
.13
.13
.13
.13
.14
.14
.14
.14
.15
.16
.17
.17
.18
.18
.18
.18
.19
.20
.20
.20
.20
.20
.20
4.5 Digitally-Controlled Oscillator (DCO) Mode
4.6 External Reference (XA/XB, REF/REFb) .
4.6.1 External Crystal (XA/XB) . . . . .
4.6.2 External Reference (REF/REFb) . .
4.7 Inputs (IN0, IN1, IN2, REF, IN3, IN4) . .
4.7.1 Input Selection . . . . . . . .
4.7.2 Manual Input Selection . . . . . .
4.7.3 Automatic Input Selection . . . . .
4.7.4 Input Configuration and Terminations .
4.7.5 Hitless Input Switching . . . . . .
4.7.6 Ramped Input Switching . . . . .
4.7.7 Glitchless Input Switching . . . . .
4.7.8 Typical Hitless Switching Scenarios .
4.7.9 Synchronizing to Gapped Input Clocks
4.8 Fault Monitoring . . . .
4.8.1 Input LOS Detection. .
4.8.2 XA/XB LOS Detection .
4.8.3 OOF Detection . . .
4.8.4 Precision OOF Monitor .
4.8.5 Fast OOF Monitor . .
4.8.6 LOL Detection . . . .
4.8.7 Interrupt Pin (INTRb) .
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4.9 Outputs . . . . . . . . . . . . . . . . . . . .
4.9.1 Output Crosspoint . . . . . . . . . . . . . . .
4.9.2 Support For 1 Hz Output . . . . . . . . . . . . .
4.9.3 Output Signal Format . . . . . . . . . . . . . .
4.9.4 Programmable Common Mode Voltage For Differential Outputs
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Preliminary Rev. 0.95 | 5
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