SA58643
Single-Pole Double-Throw (SPDT) switch
Rev. 01 — 20 November 2006
Product data sheet
1. General description
The SA58643 is a wideband RF switch fabricated in BiCMOS technology and
incorporating on-chip CMOS/TTL compatible drivers. Its primary function is to switch
signals in the frequency range DC to 1 GHz from one 50
Ω
channel to another. The switch
is activated by a CMOS/TTL compatible signal applied to the enable channel 1 pin
(ENCH1).
The extremely low current consumption makes the SA58643 ideal for portable
applications. The excellent isolation and low loss makes this a suitable replacement for
PIN diodes.
The SA58643 is available in an 8-pin TSSOP package.
2. Features
I
I
I
I
I
I
I
I
I
I
I
Wideband (DC to 1 GHz)
Low through loss (1 dB typical at 200 MHz)
Unused input is terminated internally in 50
Ω
Excellent overload capability (1 dB gain compression point +18 dBm at 300 MHz)
Low DC power (170
µA
from 5 V supply)
Fast switching (20 ns typical)
Good isolation (off channel isolation 60 dB at 100 MHz)
Low distortion (IP3 intercept +33 dBm)
Good 50
Ω
match (return loss 18 dB at 400 MHz)
Full ESD protection
Bidirectional operation
3. Applications
I
I
I
I
I
Digital transceiver front-end switch
Antenna switch
Filter selection
Video switch
FSK transmitter
NXP Semiconductors
SA58643
Single-Pole Double-Throw (SPDT) switch
4. Ordering information
Table 1.
Ordering information
Package
Name
SA58643DP
TSSOP8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm
Version
SOT505-1
Type number
5. Block diagram
input/output
output/input
output/input
ENCH1
002aab690
Fig 1. Block diagram of SA58643
6. Pinning information
6.1 Pinning
V
DD
ENCH1
GND
INPUT
1
2
3
4
002aab689
8
7
OUT1
AC_GND
GND
OUT2
SA58643DP
6
5
Fig 2. Pin configuration for TSSOP8
6.2 Pin description
Table 2.
Symbol
V
DD
ENCH1
GND
INPUT
OUT2
AC_GND
OUT1
Pin description
Pin
1
2
3, 6
4
5
7
8
Description
supply voltage
enable channel 1
ground
input
output
AC ground
output
SA58643_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 20 November 2006
2 of 16
NXP Semiconductors
SA58643
Single-Pole Double-Throw (SPDT) switch
7. Equivalent circuit
V
DD
+5 V
1
20 kΩ
8
OUT1
CONTROL
LOGIC
50
Ω
3
50
Ω
7
AC bypass
6
INPUT
ENCH1
(logic 0 level)
4
2
20 kΩ
5
OUT2
002aab711
Fig 3. Equivalent circuit
8. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
P
T
j(max)
P
INPUT_OUT1_OUT2
T
stg
[1]
Parameter
supply voltage
power dissipation
maximum junction temperature
power on pin INPUT or on
pin OUT1 or on pin OUT2
storage temperature
Conditions
T
amb
= 25
°C
(still air)
[1]
Min
−0.5
-
-
-
−65
Max
+5.5
568
150
20
+150
Unit
V
mW
°C
dBm
°C
Maximum dissipation is determined by the operating ambient temperature and the thermal resistance,
R
th(j-a)
: TSSOP8: R
th(j-a)
= 220 K/W.
9. Recommended operating conditions
Table 4.
Symbol
V
DD
T
amb
T
j
Operating conditions
Parameter
supply voltage
ambient temperature
junction temperature
SA grade
SA grade
Conditions
Min
3.0
−40
−40
Typ
-
-
-
Max
5.5
+85
+105
Unit
V
°C
°C
SA58643_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 20 November 2006
3 of 16
NXP Semiconductors
SA58643
Single-Pole Double-Throw (SPDT) switch
10. Static characteristics
Table 5.
Static characteristics
V
DD
= +5 V; T
amb
= 25
°
C; unless otherwise specified.
Symbol
I
DD
V
th
V
IH
V
IL
I
IL(ENCH1)
I
IH(ENCH1)
[1]
Parameter
supply current
threshold voltage
HIGH-level input voltage
LOW-level input voltage
LOW-level input current on pin ENCH1
HIGH-level input current on pin ENCH1
Conditions
TTL/CMOS logic
logic 1 level; enable channel 1
logic 0 level; enable channel 2
ENCH1 = 0.4 V
ENCH1 = 2.4 V
[1]
Min
40
1.1
2.0
−3.0
−1
−1
Typ
170
1.25
-
-
0
0
Max
300
1.4
V
DD
+0.8
+1
+1
Unit
µA
V
V
V
µA
µA
The ENCH1 input must be connected to a valid logic level for proper operation of the SA58643.
11. Dynamic characteristics
Table 6.
Dynamic characteristics
V
DD
= +5 V; T
amb
= 25
°
C; unless otherwise specified.
All measurements include the effects of the SA58643 evaluation board. Measurement system impedance is 50
Ω
.
Symbol Parameter
|s
21
|
2
insertion power gain
Conditions
DC to 100 MHz
500 MHz
900 MHz
|s
12
|
2
isolation
10 MHz
100 MHz
500 MHz
900 MHz
|s
22
|
2
|s
11
|
2
t
d(off)
t
f(off)
t
r(on)
V
trt(p-p)
P
L(1dB)
IP3
IP2
NF
output return loss
input return loss
turn-off delay time
turn-off fall time
turn-on rise time
peak-to-peak transient voltage
output power at 1 dB gain compression
third-order intercept point
second-order intercept point
noise figure
DC to 400 MHz
900 MHz
DC to 400 MHz
900 MHz
50 % TTL to (90 % to 10 %) RF
90 % to 10 % RF
10 % to 90 % RF
switching transients
DC to 1 GHz
100 MHz
100 MHz
Z
o
= 50
Ω
100 MHz
900 MHz
[1]
[1]
Min
-
-
-
70
-
-
24
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
1
1.4
2
80
60
50
30
20
12
17
13
20
5
5
165
+18
+33
+52
1.0
2.0
Max
-
-
2.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ns
ns
ns
mV
dBm
dBm
dBm
dB
dB
The placement of the AC bypass capacitor is critical to achieve these specifications. See
Section 13 “Application information”
for more
details.
SA58643_1
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 20 November 2006
4 of 16
NXP Semiconductors
SA58643
Single-Pole Double-Throw (SPDT) switch
12. Performance curves
002aab697
002aab698
200
I
DD
(µA)
160
0
S
21
(dB)
−2
V
DD
= 5 V
4V
3V
120
T
amb
= +85
°C
+25
°C
−40 °C
−4
80
40
−6
0
3.0
−8
4.0
5.0
V
DD
(V)
6.0
10
10
2
10
3
f (MHz)
10
4
T
amb
= +25
°C
Fig 4. Supply current versus V
DD
and temperature
−0.8
S
21
(dB)
−1.2
002aab774
Fig 5. Loss versus frequency and V
DD
0
S
21
(dB)
−2
002aab699
−4
CH2
−1.6
V
DD
= 5 V
4V
3V
−6
CH1
−2.0
10
−8
10
10
2
f (MHz)
10
3
10
2
10
3
f (MHz)
10
4
T
amb
= +25
°C
T
amb
= +25
°C;
V
DD
= 5 V
Fig 6. Loss versus frequency and V
DD
Fig 7. Loss matching versus frequency;
CH1 versus CH2
002aab700
002aab701
0
S
21
(dB)
−2
T
amb
= +85
°C
+25
°C
−40 °C
0
S
21
(dB)
−20
V
DD
= 5 V
4V
3V
−4
−40
−6
−60
−8
10
10
2
10
3
f (MHz)
10
4
−80
10
10
2
10
3
f (MHz)
10
4
V
DD
= 5 V
T
amb
= +25
°C
Fig 8. Loss versus frequency and temperature
SA58643_1
Fig 9. Isolation versus frequency and V
DD
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 20 November 2006
5 of 16
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
