MC74HC365A
Hex 3-State Noninverting
Buffer with Common
Enables
High−Performance Silicon−Gate CMOS
The MC74HC365A is identical in pinout to the LS365. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device is a high−speed hex buffer with 3−state outputs and two
common active−low Output Enables. When either of the enables is
high, the buffer outputs are placed into high−impedance states. The
HC365A has noninverting outputs.
Features
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MARKING
DIAGRAMS
16
16
1
PDIP−16
N SUFFIX
CASE 648
1
16
16
1
SOIC−16
D SUFFIX
CASE 751B
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
HC
365A
ALYWG
G
HC365AG
AWLYWW
MC74HC365AN
AWLYYWWG
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
•
Chip Complexity: 90 FETs or 22.5 Equivalent Gates
•
These are Pb−Free Devices*
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2009
December, 2009
−
Rev. 2
1
Publication Order Number:
MC74HC365A/D
MC74HC365A
OUTPUT
ENABLE 1
A0
Y0
A1
Y1
A2
Y2
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
OUTPUT
ENABLE 2
A5
Y5
A4
Y4
A3
Y3
A3
A4
A5
A2
6
10
12
14
7
9
11
13
Y2
Y3
Y4
Y5
A0
A1
2
4
3
5
Y0
Y1
Figure 1. Pin Assignment
FUNCTION TABLE
Inputs
Enable
1
L
L
H
X
Enable
2
L
L
X
H
A
L
H
X
X
Output
Y
L
H
Z
Z
1
OUTPUT ENABLE 1
15
OUTPUT ENABLE 2
PIN 16 = V
CC
PIN 8 = GND
Figure 2. Logic Diagram
X = don’t care
Z = high impedance
ORDERING INFORMATION
Device
MC74HC365ANG
MC74HC365ADG
MC74HC365ADR2G
MC74HC365ADTR2G
Package
PDIP−16
(Pb−Free)
SOIC−16
(Pb−Free)
SOIC−16
(Pb−Free)
TSSOP−16*
Shipping
†
500 Units / Rail
48 Units / Rail
2500 Units / Reel
2500 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HC365A
MAXIMUM RATINGS*
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
Value
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±
20
±
25
±
50
750
500
450
– 65 to + 150
260
Unit
V
V
V
mA
mA
mA
mW
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
T
stg
T
L
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
_C
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package:
−
6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
– 55
0
0
0
0
Max
6.0
V
CC
+ 125
1000
600
500
400
Unit
V
V
_C
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
V
out
= V
CC
– 0.1 V
|I
out
|
v
20
μA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
3.6 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
– 55 to
25_C
1.5
2.1
3.15
4.2
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.48
3.98
5.48
v
85_C
1.5
2.1
3.15
4.2
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.34
3.84
5.34
v
125_C
1.5
2.1
3.15
4.2
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.20
3.70
5.20
Unit
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V
|I
out
|
v
20
μA
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
|I
out
|
v
20
μA
V
in
= V
IH
V
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3
MC74HC365A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
OL
Parameter
Maximum Low−Level Output
Voltage
Test Conditions
V
in
= V
IL
|I
out
|
v
20
μA
V
in
= V
IL
|I
out
|
v
3.6 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
V
CC
V
2.0
4.5
6.0
3.0
4.5
6.0
6.0
6.0
– 55 to
25_C
0.1
0.1
0.1
0.26
0.26
0.26
±
0.1
±
0.5
v
85_C
0.1
0.1
0.1
0.33
0.33
0.33
±
1.0
±
5.0
v
125_C
0.1
0.1
0.1
0.40
0.40
0.40
±
1.0
±
10
μA
μA
Unit
V
I
in
I
OZ
Maximum Input Leakage Current
Maximum Three−State
Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
μA
I
CC
6.0
4
40
160
μA
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
—
—
– 55 to
25_C
120
60
24
20
220
110
44
37
220
110
44
37
60
22
12
10
10
15
v
85_C
150
75
30
26
275
140
55
47
275
140
55
47
75
28
15
13
10
15
v
125_C
180
90
36
31
330
170
66
56
330
170
66
56
90
34
18
15
10
15
Unit
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
ns
C
in
C
out
Maximum Input Capacitance
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
pF
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Buffer)*
2
f
60
+ I
CC
V
CC
.
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
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4
MC74HC365A
SWITCHING WAVEFORMS
V
CC
t
r
INPUT A
t
PLH
OUTPUT Y
t
TLH
90%
50%
10%
t
THL
90%
50%
10%
t
PHL
t
f
V
CC
GND
OUTPUT Y
OUTPUT ENABLE
50%
GND
t
PZL
50%
t
PZH
OUTPUT Y
50%
t
PHZ
10%
90%
t
PLZ
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
C
L
*
C
L
*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
LOGIC DETAIL
TO OTHER
FIVE BUFFERS
ONE OF 6
BUFFERS
V
CC
Y
INPUT A
OUTPUT ENABLE 1
OUTPUT ENABLE 2
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