LPC3152/3154
ARM926EJ microcontrollers with USB High-speed OTG,
SD/MMC, NAND flash controller, and audio codec
Rev. 1 — 31 May 2012
Product data sheet
1. General description
The NXP LPC3152/3154 combine an 180 MHz ARM926EJ-S CPU core, High-speed USB
2.0 OTG, 192 kB SRAM, NAND flash controller, flexible external bus interface, an
integrated audio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and
parallel interfaces in a single chip targeted at consumer, industrial, medical, and
communication markets. To optimize system power consumption, the LPC3152/3154
have multiple power domains and a very flexible Clock Generation Unit (CGU) that
provides dynamic clock gating and scaling.
The LPC3152/3154 are implemented as a multi-chip module with two side-by-side dies,
one for digital functions and one for analog functions, which include Power Supply Unit
(PSU), audio codec, RTC, and Li-ion battery charger.
2. Features and benefits
2.1 Key features
CPU platform
180 MHz, 32-bit ARM926EJ-S
16 kB D-cache and 16 kB I-cache
Memory Management Unit (MMU)
Internal memory
192 kB embedded SRAM
External memory interface
NAND flash controller with 8-bit ECC and AES decryption engine (LPC3154 only)
8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM
Security
AES decryption engine (LPC3154 only)
Secure one-time programmable memory for AES key storage and customer use
128 bit unique ID per device for DRM schemes
Communication and connectivity
High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY
Two I
2
S-bus interfaces
Integrated master/slave SPI
Two master/slave I
2
C-bus interfaces
Fast UART
Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA
NXP Semiconductors
LPC3152/3154
ARM926EJ microcontrollers
Three-channel 10-bit ADC
Integrated 4/8/16-bit 6800/8080 compatible LCD interface
Integrated audio codec with stereo ADC and Class AB headphone amplifier
System functions
Dynamic clock gating and scaling
Multiple power domains
Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB
On the LPC3154 only: secure booting using AES decryption engine from SPI flash,
NAND flash, SD/MMC cards, UART, or USB
DMA controller
Four 32-bit timers
Watchdog timer
PWM module
Master/slave PCM interface
Random Number Generator (RNG)
General Purpose I/O (GPIO) pins
Flexible and versatile interrupt structure
JTAG interface with boundary scan and ARM debug access
Real-Time Clock (RTC)
Power supply
Integrated power supply unit
Li-ion charger
USB charge pump
Operating voltage and temperature
Core voltage: 1.2 V
I/O voltage: 1.8 V, 3.3 V
Temperature:
40 C
to +85
C
TFBGA208 package: 12
12 mm
2
, 0.7 mm pitch
3. Ordering information
Table 1.
Ordering information
Package
Name
LPC3152FET208
LPC3154FET208
Description
Version
SOT930-1
SOT930-1
TFBGA208 TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls;
body 12 x 12 x 0.7 mm
TFBGA208 TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls;
body 12 x 12 x 0.7 mm
Type number
LPC3152_54
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 31 May 2012
2 of 94
NXP Semiconductors
LPC3152/3154
ARM926EJ microcontrollers
3.1 Ordering options
Table 2.
Ordering options for LPC3152/54
Total
SRAM
NAND
Security High-speed 10-bit
Audio
Flash
engine
USB
ADC
codec,
Controller AES
channels PSU,
RTC,
Li-ion
charger
yes
yes
no
yes
Device/
Host/OTG
Device/
Host/OTG
3
3
yes
yes
MCI
Pins
SDHC/
SDIO/
CE-ATA
Temperature
range
Type number
LPC3152FET208
LPC3154FET208
192 kB
192 kB
yes
yes
208
208
40 C
to
+85
C
40 C
to
+85
C
LPC3152_54
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 31 May 2012
3 of 94
NXP Semiconductors
LPC3152/3154
ARM926EJ microcontrollers
4. Block diagram
JTAG
TEST/DEBUG
INTERFACE
INSTRUCTION
CACHE 16 kB
DATA
CACHE 16 kB
LPC3152/3154
ARM926EJ-S
DMA
USB 2.0
HIGH-SPEED
OTG
master
slave
INTERRUPT
CONTROLLER
slave
MPMC
master
master
master
slave
slave
ROM
slave
96 kB ISRAM0
slave
96 kB ISRAM1
slave
NAND
CONTROLLER
AES
(1)
BUFFER
slave
MULTI-LAYER AHB MATRIX
MCI
SD/SDIO
slave
slave
AHB TO
APB
BRIDGE 0
WDT
SYSTEM
CONTROL
CGU
slave
AHB TO
APB
BRIDGE 1
slave
AHB TO
APB
BRIDGE 4
slave
AHB TO
APB
BRIDGE 3
slave
AHB TO
APB
BRIDGE 2
UART
LCD
SPI
PCM
IOCONFIG
10-bit ADC
EVENT
ROUTER
RNG
OTP
DMA
REGISTERS
ANALOG
DIE
I
2
S1
I
2
S0
AUDIO
CODEC
Li-ION
CHARGER
USB
CHARGE
PUMP
PSU
NAND
REGISTERS
TIMER 0/1/2/3
PWM
I
2
C0
I
2
C1
RTC
002aae095
(1) AES decryption engine available in LPC3154 only.
Fig 1.
LPC3152/3154 block diagram
LPC3152_54
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 31 May 2012
4 of 94
NXP Semiconductors
LPC3152/3154
ARM926EJ microcontrollers
5. Pinning information
5.1 Pinning
ball A1
index area
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
002aae464
2
3
4
5
6
7
8
9
10 12 14 16
11 13 15 17
LPC3152/
LPC3154
Transparent top view
Fig 2.
LPC3152/3154 pinning TFBGA208 package
Table 3.
Pin allocation table
Pin names with prefix m are multiplexed pins. See
Table 11
for pin function selection of multiplexed pins.
Pin Symbol
Row A
1
5
9
13
17
1
5
9
13
17
1
5
9
13
17
1
n.c.
VSSE_IOC
I2C_SCL0
ADC10B_GNDA
n.c.
n.c.
mNAND_RYBN0
n.c.
ADC10B_VDDA33
HP_OUTL
n.c.
mNAND_RYBN1
VPP
ADC10B_GPA1
PSU_PLAY
VDDE_IOA
2
2
6
10
14
2
6
10
14
2
6
10
14
EBI_A_1_CLE
VDDI
FFAST_IN
VSSE_IOC
-
n.c.
mGPIO9
FFAST_OUT
n.c.
-
EBI_D_10
mGPIO10
I2C_SDA0
DAC_VDDA33
-
EBI_D_11
3
3
7
11
15
3
7
11
15
3
7
11
15
EBI_D_9
VSSI
n.c.
VDDE_IOC
-
n.c.
mGPIO6
VDDA12
HP_FCR
-
n.c.
mGPIO7
VSSA12
HP_OUTR
-
EBI_D_8
4
4
8
12
16
4
8
12
16
4
8
12
16
VDDE_IOC
SPI_MISO
n.c.
HP_VDDA33
-
n.c.
SPI_MOSI
ADC10B_GPA0
HP_GNDA
-
EBI_A_0_ALE
SPI_SCK
ADC10B_GPA2
HP_FCL
-
mNAND_RYBN3
© NXP B.V. 2012. All rights reserved.
Pin Symbol
Pin Symbol
Pin Symbol
Row B
Row C
Row D
LPC3152_54
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 — 31 May 2012
5 of 94
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