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PYNQ-Z1 Board Reference Manual
Revised April 13, 2017
Overview
The PYNQ-Z1 board is designed to be used with PYNQ, a new open-source framework that enables embedded
programmers to exploit the capabilities of Xilinx Zynq All Programmable SoCs (APSoCs) without having to design
programmable logic circuits. Instead the APSoC is programmed using Python, with the code developed and tested
directly on the PYNQ-Z1. The programmable logic circuits are imported as hardware libraries and programmed
through their APIs in essentially the same way that the software libraries are imported and programmed.
The PYNQ-Z1 board is the hardware platform for the PYNQ open-source framework. The software running on the
ARM A9 CPUs includes:
A web server hosting the Jupyter Notebook design environment
The IPython kernel and packages
Linux
Base hardware library and API for the FPGA
For designers who want to extend the base system by contributing new hardware libraries, Xilinx Vivado WebPACK
tools are available free of cost.
To find out more about PYNQ, please see the project webpage at
www.pynq.io.
Here you will find materials to
help you get started and a forum for contacting the supporting community.
DOC#: 6003-410-017
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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PYNQ-Z1 Board Reference Manual
ZYNQ XC7Z020-1CLG400C
o
650MHz dual-core Cortex-A9 processor
o
DDR3 memory controller with 8 DMA
channels and 4 High Performance AXI3
Slave ports
o
High-bandwidth peripheral controllers: 1G
Ethernet, USB 2.0, SDIO
o
Low-bandwidth peripheral controller: SPI,
UART, CAN, I2C
o
Programmable from JTAG, Quad-SPI flash,
and microSD card
o
Programmable logic equivalent to Artix-7
FPGA
13,300 logic slices, each with four
6-input LUTs and 8 flip-flops
630 KB of fast block RAM
4 clock management tiles, each
with a phase-locked loop (PLL) and
mixed-mode clock manager
(MMCM)
220 DSP slices
On-chip analog-to-digital
converter (XADC)
Switches, Push-buttons, and LEDs
o
4 push-buttons
o
2 slide switches
o
4 LEDs
o
2 RGB LEDs
Expansion Connectors
o
Two standard Pmod ports
16 Total FPGA I/O
o
Arduino/chipKIT Shield connector
49 Total FPGA I/O
6 Single-ended 0-3.3V Analog
inputs to XADC
4 Differential 0-1.0V Analog inputs
to XADC
Power
o
Powered from USB or any 7V-15V external
power source
The PYNQ-Z1.
Memory
o
512MB DDR3 with 16-bit bus @
1050Mbps
o
16MB Quad-SPI Flash with factory
programmed 48-bit globally unique
EUI-48/64™
compatible identifier
o
microSD slot
USB and Ethernet
o
Gigabit Ethernet PHY
o
USB-JTAG Programming circuitry
o
USB-UART bridge
o
USB OTG PHY (supports host only)
Audio and Video
o
HDMI sink port (input)
o
HDMI source port (output)
o
Microphone with PDM interface
o
PWM driven mono audio output with
3.5mm jack
The board can be purchased stand-alone or with an accessory kit that contains a 12V/3A power adapter, 10 foot
Ethernet cable, USB A to Micro-B cable, and an 8GB, speed class 10 microSD card loaded with the PYNQ image is
available. For more information on purchasing, see the
PYNQ Product Page.
1
Power Supplies
The PYNQ-Z1 can be powered from the Digilent USB-JTAG-UART port (J14) or from some other type of power
source such as a battery or external power supply. Jumper JP5 (near the power switch) determines which power
source is used.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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PYNQ-Z1 Board Reference Manual
A USB 2.0 port can deliver maximum 0.5A of current according to the specifications. This should provide enough
power for lower complexity designs. More demanding applications, including any that drive multiple peripheral
boards or other USB devices, might require more power than the USB port can provide. In this case, power
consumption will increase until it’s limited by the USB host. This limit varies a lot between manufacturers
of host
computers and depends on many factors. When in current limit, once the voltage rails dip below their nominal
value, the Zynq is reset by the Power-on Reset signal and power consumption returns to its idle value. Also, some
applications may
need to run without being connected to a PC’s USB port. In these instances an external power
supply or battery can be used.
An external power supply (e.g. wall wart) can be used by plugging it into the power jack (J18) and setting jumper
JP5 to “REG”. The
supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 7VDC to
15VDC. Suitable supplies can be purchased from the Digilent website or through catalog vendors like DigiKey.
Power supply voltages above 15VDC might cause permanent damage. A suitable external power supply is included
with the PYNQ-Z1 accessory kit.
Similar to using an external power supply, a battery can be used to power the PYNQ-Z1 by attaching it to the shield
connector and setting jumper JP5 to “REG”. The positive
terminal of the battery must be connected to the pin
labeled “VIN” on J7, and the negative terminal must be connected to the pin labeled
GND on J7.
The on-board Texas Instruments TPS65400 PMU creates the required 3.3V, 1.8V, 1.5V, and 1.0V supplies from the
main power input. Table 1.1 provides additional information (typical currents depend strongly on Zynq
configuration and the values provided are typical of medium size/speed designs).
All on-board power supplies are enabled or disabled by the power switch SW4. The power indicator LED (LD13) is
on when all the supply rails reach their nominal voltage.
Supply
3.3V
1.0V
1.5V
1.8V
Circuits
FPGA I/O, USB ports, Clocks, Ethernet, SD slot, Flash, HDMI
FPGA, Ethernet Core
DDR3
FPGA Auxiliary, Ethernet I/O, USB Controller
Table 1.1. PYNQ-Z1 power supplies.
Current (max/typical)
1.6A/0.1A to 1.5A
2.6A/0.2A to 2.1A
1.8A/0.1A to 1.2A
1.8A/0.1A to 0.6A
2
Zynq APSoC Architecture
The Zynq APSoC is divided into two distinct subsystems: The Processing System (PS) and the Programmable Logic
(PL). Figure 2.1 shows an overview of the Zynq APSoC architecture, with the PS colored light green and the PL in
yellow. Note that the PCIe Gen2 controller and Multi-gigabit transceivers are not available on the Zynq-7020
device.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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PYNQ-Z1 Board Reference Manual
Figure 2.1. Zynq APSoC architecture.
The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several dedicated ports and buses
that tightly couple it to the PS. The PL also does not contain the same configuration hardware as a typical 7-series
FPGA, and it must be configured either directly by the processor or via the JTAG port.
The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9
processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and
various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed
I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can
instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are
connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers
that
are addressable in the processors’ memory space. The programmable logic is also connected to the
interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain
addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors
(connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory.
There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a
complete and thorough description, refer to the
Zynq Technical Reference manual.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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Table 2.1 depicts the external components connected to the MIO pins of the PYNQ-Z1. The Zynq Presets File found
on the
PYNQ-Z1 Resource Center
can be imported into EDK and Vivado Designs to properly configure the PS to
work with these peripherals.
MIO 500 3.3 V
Pin
0 (N/C)
1
2
3
4
5
6
7 (N/C)
8
9
10
11
12
13 (N/C)
14
15
Peripherals
ENET 0
SPI Flash
CS
DQ0
DQ1
DQ2
DQ3
SCLK
SLCK FB
USB 0
Shield
UART 0
Ethernet Reset
Ethernet Interrupt
USB Over Current
Shield Reset
UART Input
UART Output
MIO 501 1.8V
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Peripherals
ENET 0
TXCK
TXD0
TXD1
TXD2
TXD3
TXCTL
RXCK
RXD0
RXD1
RXD2
RXD3
RXCTL
USB 0
SDIO 0
DATA4
DIR
STP
NXT
DATA0
DATA1
DATA2
DATA3
CLK
DATA5
DATA6
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Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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