240Pin DDR3L 1.35V 1866 SO-DIMM
4GB Based on 512Mx8
AQD-SD3L4GN18-MG
Description
AQD-SD3L4GN18-MG is a DDR3L 1866Mbps SO-DIMM
high-speed, memory module that use 8pcs of 512Mx 64
bits DDR3L SDRAM in FBGA package and a 4K bits
serial EEPROM on a 240-pin printed circuit board.
AQD-D3L4GN18-MG is a Dual In-Line Memory Module
and is intended for mounting into 240-pin edge connector
sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
CK0, /CK0,CK1, /CK1
CKE0, CKE1
ODT0, ODT1
/S0, /S1
/RAS
/CAS
/WE
DM0~DM7
VDD
VDDQ
V
REF
DQ
V
REF
CA
V
DD
SPD
SA0~SA2
EEPROM
SCL
SDA
VSS
/RESET
VTT
NC
I2C serial bus clock for EEPROM
I2C serial bus data for EEPROM
Ground
Set DRAMs Known State
DRAM I/O termination supply
No Connection
Clock Input. (Differential pair)
Clock Enable Input.
On-die termination control line
DIMM rank select lines.
Row address strobe
Column address strobe
Write Enable
Data masks/high data strobes
Core power supply
I/O driver power supply
DQ reference supply
Command/address reference
supply
SPD EEPROM power supply
I2C serial bus address select for
Pin Identification
Symbol
A0~A14, BA0~BA2
DQ0~DQ63
DQS0~DQS7
/DQS0~/DQS7
Function
Address/Bank input
Bi-direction data bus.
Data strobes
Differential Data strobes
Features
Lead-free and Halogen free products are RoHS
Compliant
JEDEC standard 1.35V(1.28V~1.45V) Power supply
Backward compatible for 1.5V(1.425V~1.575V)
VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
MRS Cycle with address key programs
- CAS Latency( 5,6,7,8,9,10,11,12,13)
- Burst Length (BL):8 and 4 with Burst Chop(BC)
Bi-directional, differential data strobe (DQS and /DQS)
Differential clock input (CK, /CK) operation
8 bit pre-fetch
Double-data-rate architecture; two data transfers per
clock cycle
Internal calibration through ZQ pin
On Die Termination with ODT pin
Auto refresh and self refresh
Average Refresh Period 7.8us at lower than TCASE
85°C, 3.9us at 85°C < TCASE ≤ 95°C
2
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