24AA02H/24LC02BH
2K I
2
C
™
Serial EEPROM with Half-Array Write-Protect
Device Selection Table
Part
Number
24AA02H
24LC02BH
Note 1:
V
CC
Range
1.7-5.5
2.5-5.5
Max. Clock
Frequency
400 kHz
(1)
400 kHz
Temp.
Ranges
I
I, E
Description:
The Microchip Technology Inc. 24AA02H/24LC02BH
(24XX02H*) is a 2 Kbit Electrically Erasable PROM.
The device is organized as one block of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and active currents of only 1
μA
and 1 mA, respec-
tively. The 24XX02H also has a page write capability for
up to 8 bytes of data. The 24XX02H is available in the
standard 8-pin PDIP, surface mount SOIC, TSSOP, 2x3
TDFN and MSOP packages, and is also available in
the 5-lead SOT-23 and SC-70 packages.
100 kHz for V
CC
<2.5V
Features:
• Single Supply with Operation down to 1.7V for
24AA02H Devices, 2.5V for 24LC02BH Devices
• Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby current 1
μA,
max. (I-temp)
• 2-Wire Serial Interface, I
2
C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 8-Byte Page Write Buffer
• Hardware Write-Protect for Half-Array (80h-FFh)
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
TDFN, MSOP, 5-lead SOT-23 and SC-70
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Package Types
PDIP, MSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
SOT-23/SC-70
SCL
Vss
SDA
Note:
1
2
3
4
Vcc
5
WP
A0 1
A1 2
A2 3
V
SS
4
V
CC
WP
SCL
A0
A1
A2
SOIC, TSSOP
1
2
3
4
TDFN
8 V
CC
7 WP
6 SCL
5 SDA
8
7
6
5
V
CC
WP
SCL
SDA
SDA V
SS
Pins A0, A1 and A2 are not used by the 24XX02H
(no internal connections).
Block Diagram
WP
HV
Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
I/O
SCL
YDEC
SDA
V
CC
V
SS
Sense Amp.
R/W Control
©
2008 Microchip Technology Inc.
DS22105A-page 1
24AA02H/24LC02BH
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V
Automotive (E): V
CC
= +2.5V to 5.5V
Min.
—
0.7 V
CC
—
0.05 V
CC
Max.
—
—
0.3 V
CC
—
Units
—
V
V
V
—
—
—
(Note)
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
Conditions
DC CHARACTERISTICS
Param.
No.
D1
D2
D3
D4
Sym.
—
V
IH
V
IL
V
HYS
Characteristic
A0, A1, A2, SCL, SDA
and WP pins:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
D5
D6
D7
D8
D9
D10
Note:
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
Write
I
CCS
—
—
—
—
—
—
—
0.40
±1
±1
10
1
3
1
V
μA
μA
pF
mA
mA
μA
I
OL
= 3.0 ma @ V
CC
= 4.5V
I
OL
= 2.1 ma @ V
CC
= 2.5V
V
IN
= V
SS
or V
CC
, WP = V
SS
V
OUT
= V
SS
or V
CC
V
CC
= 5.0V
(Note)
T
A
= 25°C, f = 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V
V
CC
= 5.5V, SCL = SDA = V
CC
WP = V
SS
, A0, A1, A2 = V
SS
I
CC
Read Operating current
Standby current
This parameter is periodically sampled and not 100% tested.
DS22105A-page 2
©
2008 Microchip Technology Inc.
24AA02H/24LC02BH
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V
Automotive (E): V
CC
= +2.5V to 5.5V
Characteristic
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
(Note 1)
SDA and SCL fall time
(Note 1)
Min.
—
—
4000
600
4700
1300
—
—
—
—
4000
600
4700
600
0
250
100
4000
600
4000
600
4700
600
—
—
1300
4700
—
—
1M
Max.
100
400
—
—
—
—
1000
300
1000
300
—
—
—
—
—
—
—
—
—
—
—
—
—
3500
900
—
—
50
5
—
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
Conditions
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
(Note 2)
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
1.7V
≤
V
CC
< 2.5V
2.5V
≤
V
CC
≤
5.5V
(Note 1 and Note 3)
—
25°C, V
CC
= 5.5V, Block mode
(Note 4)
AC CHARACTERISTICS
Param.
Symbol
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
Start condition hold time
T
SU
:
STA
Start condition setup time
T
HD
:
DAT
Data input hold time
T
SU
:
DAT
T
SU
:
STO
T
SU
:
WP
T
HD
:
WP
T
AA
T
BUF
Data input setup time
Stop condition setup time
WP setup time
WP hold time
Output valid from clock
(Note 2)
Bus free time: Time the bus
must be free before a new
transmission can start
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or
page)
Endurance
16
17
18
T
SP
T
WC
—
ns
ms
cycles
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
©
2008 Microchip Technology Inc.
DS22105A-page 3
24AA02H/24LC02BH
FIGURE 1-1:
BUS TIMING DATA
5
2
D4
4
SCL
SDA
In
7
6
16
3
8
9
10
13
SDA
Out
(protected)
(unprotected)
14
WP
11
12
DS22105A-page 4
©
2008 Microchip Technology Inc.
24AA02H/24LC02BH
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
A0
A1
A2
V
SS
SDA
SCL
WP
V
CC
PIN FUNCTION TABLE
PDIP
1
2
3
4
5
6
7
8
SOIC
1
2
3
4
5
6
7
8
TSSOP
1
2
3
4
5
6
7
8
DFN
1
2
3
4
5
6
7
8
MSOP
1
2
3
4
5
6
7
8
SOT23
—
—
—
2
3
1
5
4
SC-70
—
—
—
2
3
1
5
4
Description
Not Connected
Not Connected
Not Connected
Ground
Serial Address/Data I/O
Serial Clock
Write-Protect Input
+1.7V to 5.5V Power
Supply
2.1
A0, A1, A2
2.4
Write-Protect (WP)
The A0, A1 and A2 pins are not used by the 24XX02H.
They may be left floating or tied to either V
SS
or V
CC
.
The WP pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory
00-FF
).
If tied to V
CC
, write operations are inhibited. Half of the
memory will be write-protected (80h-FFh). Read
operations are not affected.
2.2
Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.3
Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
©
2008 Microchip Technology Inc.
DS22105A-page 5
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