TDA8035
High integrated and low power smart card interface
Rev. 3.1 — 30 June 2016
Product data sheet
1. General description
The TDA8035 is the cost efficient successor of the established integrated contact smart
card reader IC TDA8024. It offers a high level of security for the card by performing
current limitation, short-circuit detection, ESD protection as well as supply supervision.
The current consumption during the standby mode of the contact reader is very low as it
operates in the 3 V supply domain. The TDA8035 is therefore the ideal component for a
power efficient contact reader.
2. Features and benefits
2.1 Protection of the contact smart card
Thermal and short-circuit protection on all card contacts
V
CC
regulation:
5 V, 3 V, 1.8 V
5 % on 2 220 nF multilayer ceramic capacitors with low ESR
Current spikes of 40 nA/s (V
CC
= 5 V and 3 V) or 15 nA/s (V
CC
= 1.8 V) up to
20 MHz, with controlled rise and fall times. Filtered overload detection is
approximately 120 mA.
Automatic activation and deactivation sequences initiated by software or by hardware
in the event of a short-circuit, card take-off, overheating, falling V
REG
V
DD(INTF),
V
DDP
Enhanced card-side ElectroStatic Discharge (ESD) protection of (> 8 kV)
Supply supervisor for killing spikes during power on and off:
threshold internally fixed
externally by a resistor bridge
2.2 Easy integration into your contact reader
SW compatible to TDA8024 and TDA8034
5 V, 3 V, 1.8 V smart card supply
DC-to-DC converter for V
CC
generation separately powered from 2.7 V to 5.5 V supply
(V
DDP
and GNDP)
Very low power consumption in Deep Shutdown mode
Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8)
External clock input up to 26 MHz
Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with
synchronous frequency changes of f
XTAL
, fXTAL/2, fXTAL/4 or fXTAL/8
Non-inverted control of pin RST using pin RSTIN
Built-in debouncing on card presence contact
Multiplexed status signal using pin OFFN
NXP Semiconductors
TDA8035
High integrated and low power smart card interface
Chip Select digital input for parallel operation of several TDA8035 ICs.
2.2.1 Other
HVQFN32 package
Compliant with ISO 7816, NDS and EMV 4.3
(*)
payment systems
(*)
for C2 version
3. Applications
Pay TV
Electronic payment
Identification
IC card readers for banking
4. Quick reference data
Table 1.
Quick reference data
V
DDP
= 3.3 V; V
DD(INTF)
= 3.3 V; f
Xtal
= 10 MHz; GND = 0 V; T
amb
= 25
C; unless otherwise specified
Symbol
Supply
V
DDP
V
DD(INTF)
I
DDP
power supply voltage
interface supply voltage
power supply current
deep shutdown mode;
f
XTAL
= stopped;
shutdown mode;
f
XTAL
= stopped;
active mode; V
CC
= +5 V
CLK = f
XTAL
/2; no load
active mode; CLK = f
XTAL
/2;
V
CC
= +5 V; I
CC
= 65 mA
active mode; CLK = f
XTAL
/2;
V
CC
= +3 V; I
CC
= 65 mA
active mode; CLK = f
XTAL
/2;
V
CC
= +1.8 V; I
CC
= 35 mA
I
DD(INTF)
interface supply current
deep shutdown mode;
f
XTAL
= stopped;
present card
shutdown mode;
f
XTAL
= stopped;
present card
Internal supply voltage
V
DD
supply voltage
1.62
1.8
1.98
V
-
-
-
-
-
-
-
-
-
-
5
220
160
120
1
mA
mA
mA
mA
A
-
300
500
A
2.7
1.6
-
3.3
3.3
0.1
5.5
3.6
3
V
V
A
Parameter
Conditions
Min
Typ
Max
Unit
-
-
1
A
TDA8035
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — June 30, 2016
2 of 32
NXP Semiconductors
TDA8035
High integrated and low power smart card interface
Table 1.
Quick reference data
…continued
V
DDP
= 3.3 V; V
DD(INTF)
= 3.3 V; f
Xtal
= 10 MHz; GND = 0 V; T
amb
= 25
C; unless otherwise specified
Symbol
V
CC
Parameter
supply voltage
Conditions
5 V card; DC ICC < 65 mA
5 V card; AC current spikes
of 40 nA/s
3 V card; DC I
CC
< 65 mA
3 V card; AC current spikes
of 40 nA/s
1.8 V card; DC I
CC
< 35 mA
1.8 V card; AC current
spikes of 15 nA/s
V
ripple(p-p)
I
CC
General
t
deact
P
tot
T
amb
deactivation time
total power dissipation
ambient temperature
total sequence
35
-
25
90
-
-
250
0.45
+85
s
W
C
peak-to-peak ripple voltage
supply current
from 20 kHz to 200 MHz
V
CC = 5 V or 3 V
V
CC = 1.8 V
Min
4.75
4.65
2.85
2.76
1.71
1.66
-
-
-
Typ
5.0
5.0
-
-
-
-
-
-
-
Max
5.25
5.25
3.15
3.24
1.89
1.94
300
65
35
Unit
V
V
V
V
V
V
mV
mA
mA
Card supply voltage: pin VCC
5. Ordering information
The TDA8035 is available in 2 versions, which have the same functionalities. The C2
version is compliant with the EMVC0 4.3 standard.
Table 2.
Ordering information
Package
Name
TDA8035HN/C1
TDA8035HN/C1/S1
TDA8035HN/C2/S1
HVQFN32
HVQFN32
HVQFN32
Description
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5
5
0.85 mm
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5
5
0.85 mm;
[1]
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5
5
0.85 mm;
[1]
Version
SOT617-7
SOT617-7
SOT617-7
Type number
[1]
copper wiring
TDA8035
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — June 30, 2016
3 of 32
NXP Semiconductors
TDA8035
High integrated and low power smart card interface
6. Block diagram
V
DD(INTF)
V
DDP
330 nF
100 nF
10 μF
100 nF
330 nF
100 nF
V
DD(INTF)
CS
CMDVCCN
EN_5V/3VN
EN_1.8VN
RSTIN
CLKDIV1
CLKDIV2
HOST
INTERFACE
I/OUC
UC
AUX1UC
AUX2UC
H
Z
LATCH
deep
shutdown
PORADJ
V
REG
GND
V
DDP
GNDP
SAP
SAM SBP
SBM
INTERNAL
REGULATOR
DEEP
SHUTDOWN
VUP
DCDC
CONVERTER
1 μF
V
CC
INPUT SENSE
SUPERVISOR
DEEP SHUTDOWN
RST
CLK
BANDGAP
AUX1
AUX2
INTERNAL
OSCILLATOR
I/O
C6
C7
configurations
bus for smartcard
reader interface
interuption
THERMAL
PROTECTION
DIGITAL
SEQUENCER
CRYSTAL
OSCILLATOR
XTAL1
XTAL2
C8
C2
C3
C4
C5
C1
reset and
supalarm
ISO7816
READER
INTERFACE
GNDC
2
×
220 nF
TDA8035
V
DD(INTF)
OFFN
H
Z
PRESN
001aan745
Fig 1.
Block diagram
TDA8035
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — June 30, 2016
4 of 32
NXP Semiconductors
TDA8035
High integrated and low power smart card interface
7. Pinning information
7.1 Pinning
31 AUX1UC
32 AUX2UC
30 PRESN
I/OUC
PORADJ
CMDVCCN
V
DD(INTF)
CLKDIV1
CLKDIV2
EN_5V/3VN
EN_1.8VN
1
2
3
4
5
6
7
8
OFFN 10
XTAL1 12
XTAL2 13
V
REG
14
SAM 15
GNDP 16
GND 11
9
28 I/O
terminal 1
index area
25 GNDC
24 CLK
23 RST
22 V
CC
21 VUP
20 SAP
19 SBP
18 V
DDP
17 SBM
001aan746
27 AUX2
TDA8035
RSTN
Transparent top view
Fig 2.
Pin configuration HVQFN32
7.2 Pin description
Table 3.
Symbol
I/OUC
PORADJ
CMDVCCN
V
DD(INTF)
CLKDIV1
CLKDIV2
EN_5V/3VN
EN_1.8 VN
RSTIN
OFFN
GND
XTAL1
XTAL2
V
REG
SAM
GNDP
TDA8035
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Supply
V
DD(INTF)
V
DD(INTF)
V
DD(INTF)
V
DD(INTF)
V
DD(INTF)
V
DD(INTF)
V
DD(INTF)
V
DD(INTF)
V
DD(INTF)
V
DD(INTF)
-
V
DD(INTF)
V
DD(INTF)
V
DDP
V
DDP
-
Type
I/O
I
I
supply
I
I
I
I
I
O
supply
I
O
supply
I/O
supply
Description
host data I/O line (internal 10 k pull-up resistor to V
DD(INTF)
)
Input for V
DD(INTF)
supervisor. PORADJ threshold can be changed with an
external R bridge
start activation sequence input from the host (active LOW)
interface supply voltage
control with CLKDIV2 for choosing CLK frequency (see
Table 4)
control with CLKDIV1 for choosing CLK frequency (see
Table 4)
control signal for selecting V
CC
= 5 V (HIGH) or V
CC
= 3 V (LOW) if
EN_1.8 VN = High
control signal for selecting V
CC
= 1.8 V (low)
card reset input from the host (active HIGH)
NMOS interrupt to the host (active LOW) with 10 k internal pull-up resistor to
V
DD(INTF)
(See fault detection)
ground
crystal connection 1
crystal connection 2
Internal supply voltage
DC-to-DC converter capacitor; connected between SAM and SAP; C = 330 nF
or 100 nF (see
Figure 13)
with ESR < 100 m at Freq=100kHz
DC-to-DC converter power supply ground
© NXP Semiconductors N.V. 2016. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 3 — June 30, 2016
26 AUX1
29 CS
5 of 32
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