GTL2003
8-bit bidirectional low voltage translator
Rev. 2 — 3 July 2012
Product data sheet
1. General description
The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide
high-speed voltage translation with low ON-state resistance and minimal propagation
delay. The GTL2003 provides eight NMOS pass transistors (Sn and Dn) with a common
gate (GREF) and a reference transistor (SREF and DREF). The device allows
bidirectional voltage translations between 0.8 V and 5.0 V without use of a direction pin.
Voltage translation below 0.8 V can be achieved when properly biased. For more
information, refer to application note
AN11127
(Ref.
1).
When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn
port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by
the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to V
DD1
by the pull-up resistors. This functionality allows a seamless translation between higher
and lower voltages selected by the user, without the need for directional control.
All transistors have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical, SREF and DREF can be
located on any of the other eight matched Sn/Dn transistors, allowing for easier board
layout. The translator's transistors provide excellent ESD protection to lower voltage
devices and at the same time protect less ESD-resistant devices.
2. Features and benefits
8-bit bidirectional low voltage translator
Allows voltage level translation between 0.8 V, 0.9 V, 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V,
3.3 V, and 5 V buses which allows direct interface with GTL, GTL+, LVTTL/TTL and
5 V CMOS levels
Provides bidirectional voltage translation with no direction pin
Low 6.5
ON-state resistance (R
on
) between input and output pins (Sn/Dn)
Supports hot insertion
No power supply required: will not latch up
5 V tolerant inputs
Low standby current
Flow-through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 2000 V HBM per JESD22-A114, and 1000 V CDM per
JESD22-C101
Packages offered: TSSOP20, DHVQFN20
NXP Semiconductors
GTL2003
8-bit bidirectional low voltage translator
3. Applications
Any application that requires bidirectional or unidirectional voltage level translation
from any voltage from 0.8 V to 5.0 V to any voltage from 0.8 V to 5.0 V
The open-drain construction with no direction pin is ideal for bidirectional low voltage
(for example, 0.8 V, 0.9 V, 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I
2
C-bus port
translation to the normal 3.3 V and/or 5.0 V I
2
C-bus signal levels or GTL/GTL+
translation to LVTTL/TTL signal levels.
4. Ordering information
Table 1.
Ordering information
Name
GTL2003BQ
Description
Version
SOT764-1
Type number Package
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
GTL2003PW
SOT360-1
4.1 Ordering options
Table 2.
Ordering options
Topside mark
2003
GTL2003
Temperature range
40 C
to +85
C
40 C
to +85
C
Type number
GTL2003BQ
GTL2003PW
5. Functional diagram
DREF
GREF
D1
D8
SREF
S1
S8
002aac641
Fig 1.
Functional diagram
GTL2003
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 July 2012
2 of 24
NXP Semiconductors
GTL2003
8-bit bidirectional low voltage translator
6. Pinning information
6.1 Pinning
20 GREF
19 DREF
18 D1
17 D2
16 D3
15 D4
14 D5
13 D6
12 D7
S8 10
D8 11
GND
2
3
4
5
6
7
8
9
1
SREF
S1
GND
SREF
S1
S2
S3
S4
S5
S6
S7
1
2
3
4
5
6
7
8
9
20 GREF
19 DREF
18 D1
17 D2
16 D3
15 D4
14 D5
13 D6
12 D7
11 D8
002aac639
terminal 1
index area
S2
S3
S4
S5
S6
S7
GTL2003BQ
GTL2003PW
S8 10
002aac640
Transparent top view
Fig 2.
Pin configuration for TSSOP20
Fig 3.
Pin configuration for DHVQFN20
6.2 Pin description
Table 3.
Symbol
GND
SREF
S1 to S8
D1 to D8
DREF
GREF
[1]
Pin description
Pin
1
[1]
2
3, 4, 5, 6, 7, 8, 9, 10
18, 17, 16, 15, 14, 13, 12, 11
19
20
Description
ground (0 V)
source of reference transistor
Port S1 to Port S8
Port D1 to Port D8
drain of reference transistor
gate of reference transistor
DHVQFN20 package die supply ground is connected to both GND pin and exposed center pad. GND pin
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper heat conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
GTL2003
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 July 2012
3 of 24
NXP Semiconductors
GTL2003
8-bit bidirectional low voltage translator
7. Functional description
Refer also to
Figure 1 “Functional diagram”.
7.1 Function selection
Table 4.
Function selection, HIGH-to-LOW translation
Assumes Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care
GREF
[1]
H
H
H
L
[1]
[2]
[3]
[4]
DREF
H
H
H
L
SREF
0V
V
T[2]
V
T[2]
0 V
V
T[2]
Input Dn
X
H
L
X
Output Sn
X
V
T[2][3]
L
[4]
X
Transistor
off
on
on
off
GREF should be at least 1.5 V higher than SREF for best translator operation.
V
T
is equal to the SREF voltage.
Sn is not pulled up or pulled down.
Sn follows the Dn input LOW.
Table 5.
Function selection, LOW-to-HIGH translation
Assumes Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care
GREF
[1]
H
H
H
L
[1]
[2]
[3]
[4]
DREF
H
H
H
L
SREF
0V
V
T[2]
V
T[2]
0 V
V
T[2]
Input Sn
X
V
T[2]
L
X
Output Dn
X
H
[3]
L
[4]
X
Transistor
off
nearly off
on
off
GREF should be at least 1.5 V higher than SREF for best translator operation.
V
T
is equal to the SREF voltage.
Dn is pulled up to V
DD1
through an external resistor.
Dn follows the Sn input LOW.
GTL2003
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 July 2012
4 of 24
NXP Semiconductors
GTL2003
8-bit bidirectional low voltage translator
8. Application design-in information
8.1 Bidirectional translation
For the bidirectional clamping configuration, higher voltage to lower voltage or lower
voltage to higher voltage, the GREF input must be connected to DREF and both pins
pulled to HIGH side V
DD1
through a pull-up resistor (typically 200 k). A filter capacitor on
DREF is recommended. The processor output can be totem pole or open-drain (pull-up
resistors may be required) and the chip set output can be totem pole or open-drain
(pull-up resistors are required to pull the Dn outputs to V
DD1
). However, if either output is
totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs
must be controlled by some direction control mechanism to prevent HIGH-to-LOW
contentions in either direction. If both outputs are open-drain, no direction control is
needed. The opposite side of the reference transistor (SREF) is connected to the
processor core power supply voltage. When DREF is connected through a 200 k
resistor to a 3.3 V to 5.5 V V
DD1
supply and SREF can be set between 0.8 V to
(V
DD1
1.5 V), without the need for pull-up resistors on the low voltage side. The output of
each Sn will have a maximum output voltage equal to SREF and the output of each Dn
has a maximum output voltage equal to V
DD1
. It is recommended that V
DD1
be greater
than 1.5 V for proper operation.
1.8 V
1.5 V
1.2 V
1.0 V
0.8 V
5V
200 kΩ
GTL2002
GND
V
CORE
CPU I/O
S2
D2
SREF
S1
GREF
DREF
D1
totem pole or
open-drain I/O
V
DD1
CHIPSET I/O
increase bit size
by using 8-bit GTL2003,
10-bit GTL2010,
or 22-bit GTL2000
3.3 V
V
DD2
S3
S4
S5
Sn
D3
CHIPSET I/O
D4
D5
Dn
002aac642
Typical bidirectional voltage translation.
Fig 4.
Bidirectional translation to multiple higher voltage levels such as an I
2
C-bus
application
GTL2003
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 July 2012
5 of 24
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
