LTC4305
2-Channel,
2-Wire Bus Multiplexer with
Capacitance Buffering
FEATURES
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■
DESCRIPTIO
■
■
■
■
■
■
■
■
1:2 2-Wire Multiplexer/Switch
Connect SDA and SCL Lines with 2-Wire Bus
Commands
Supply Independent Bidirectional Buffer for SDA
and SCL Lines Increases Fan-Out
Programmable Disconnect from Stuck Bus
Compatible with I
2
C and SMBus Standards
Rise Time Accelerator Circuitry
SMBus Compatible ALERT Response Protocol
Prevents SDA and SCL Corruption During Live Board
Insertion and Removal from Backplane
±10kV
Human Body Model ESD Ruggedness
16-Lead (4mm
×
5mm) DFN and SSOP Packages
The LTC
®
4305 is a 2-channel, 2-wire bus multiplexer with
bus buffers to provide capacitive isolation between the
upstream bus and downstream buses. Through software
control, the LTC4305 connects the upstream 2-wire bus
to any desired combination of downstream channels.
Each channel can be pulled up to a supply voltage ranging
from 2.2V to 5.5V, independent of the LTC4305 supply
voltage. The downstream channels are also provided with
an ALERT1–ALERT2 inputs for fault reporting.
Programmable timeout circuitry disconnects the down-
stream buses if the bus is stuck low. When activated, rise
time accelerators source currents into the 2-wire bus pins
to reduce rise time. Driving the ENABLE pin low restores
all features to their default states. Three address pins
provide 27 distinct addresses.
The LTC4305 is available in 16-lead (4mm
×
5mm) DFN
and SSOP packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Patent Pending.
APPLICATIO S
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■
■
Nested Addressing
5V/3.3V Level Translator
Capacitance Buffer/Bus Extender
TYPICAL APPLICATIO
2.5V
3.3V
A Level-Shifting and Nested Addressing Application
I
2
C Bus Waveforms
0.01µF
10k
10k
10k
V
CC
SCLIN
MICRO-
CONTROLLER
SDAIN
ALERT
SCL1
SDA1
ALERT1
5V
LTC4305
ADR2
ADR1
ADR0
GND
SCL2
SDA2
ALERT2
4305 TA01
V
CC
= 3.3V
10k
10k
10k
SCLIN
2V/DIV
SFP
MODULE #1
ADDRESS = 1111 000
SCL1
2V/DIV
10k
10k
10k
SFP
MODULE #2
ADDRESS = 1111 000
SCL2
2V/DIV
500ns/DIV
ADDRESS = 1000 100
U
VBACK = 2.5V
VCARD1 = 3.3V
VCARD2 = 5V
4305 TA01b
U
U
4305f
1
LTC4305
ABSOLUTE
AXI U RATI GS
(Note 1)
Operating Temperature Range
LTC4305C ............................................... 0°C to 70°C
LTC4305I ............................................. –40°C to 85°C
Storage Temperature Range
DHD Package .................................... –65°C to 125°C
GN Package ....................................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
GN Package ...................................................... 300°C
Supply Voltage (V
CC
) ................................... –0.3V to 7V
Input Voltages (ADR0, ADR1, ADR2,
ENABLE, ALERT1, ALERT2) .................... –0.3V to 7V
Output Voltages (ALERT, READY) ............... –0.3V to 7V
Input/Output Voltages (SDAIN, SCLIN,
SCL1, SDA1, SCL2, SDA2) ...................... –0.3V to 7V
Output Sink Current (SDAIN, SCLIN, SCL1,
SDA1, SCL2, SDA2, ALERT, READY) ............... 10mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ALERT2
ALERT
SDAIN
GND
SCLIN
ENABLE
V
CC
ADRO
1
2
3
4
5
6
7
8
17
16 SCL2
15 SDA2
14 ALERT1
13 SDA1
12 SCL1
11 READY
10 ADR2
9
ADR1
DHD PACKAGE
16-LEAD (4mm
×
5mm) PLASTIC DFN
EXPOSED PAD (PIN 17) PCB CONNECTION OPTIONAL
MUST BE CONNECTED TO PCB TO OBTAIN
θ
JA
= 43°C/W OTHERWISE
θ
JA
= 140°C/W. T
JMAX
= 125°C
ORDER PART NUMBER
LTC4305CDHD
LTC4305IDHD
DHD PART MARKING
4305
4305
Order Options
Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marketing:
http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL
V
CC
I
CC
I
CC ENABLE
= 0V
V
UVLOU
V
UVLOHYST
PARAMETER
Input Supply Range
Input Supply Current
Input Supply Current
UVLO Upper Threshold Voltage
UVLO Threshold Hysteresis Voltage
Power Supply/Start-Up
The
●
denotes specifications which apply over the full specified temperature
range, otherwise specifications are at T
A
= 25°C. V
CC
= 3.3V unless otherwise noted.
CONDITIONS
●
Downstream Connected, V
CC
= 5.5V
SCL Bus Low, SDA Bus High
V
ENABLE
= 0V, V
CC
= 5.5V
2
U
U
W
W W
U
W
TOP VIEW
ALERT2
ALERT
SDAIN
GND
SCLIN
ENABLE
V
CC
ADR0
1
2
3
4
5
6
7
8
16 SCL2
15 SDA2
14 ALERT1
13 SDA1
12 SCL1
11 READY
10 ADR2
9
ADR1
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
T
JMAX
= 125°C,
θ
JA
= 135°C/W
ORDER PART NUMBER
LTC4305CGN
LTC4305IGN
GN PART MARKING
4305
4305I
MIN
2.7
TYP
MAX
5.5
UNITS
V
mA
mA
V
mV
4305f
●
●
●
●
5.2
1.25
2.3
100
2.5
175
8
2.5
2.7
250
LTC4305
The
●
denotes specifications which apply over the full specified temperature
range, otherwise specifications are at T
A
= 25°C. V
CC
= 3.3V unless otherwise noted.
SYMBOL
V
TH EN
V
EN HYST
t
PHL EN
t
PLH EN
I
IN EN
V
LOW READY
I
OFF READY
ALERT
V
ALERT(OL)
I
OFF, ALERT
I
IN, ALERT1–2
V
ALERT1–2(IN)
V
ALERT1–2(HY)
ALERT Output Low Voltage
ALERT Off State Input Leakage Current
ALERT1–ALERT2 Input Current
ALERT1–ALERT2 Pin Input Falling
Threshold Voltages
ALERT1–ALERT2 Pin Input Threshold
Hysteresis Voltages
Initial Slew Requirement to Activate
Rise Time Accelerator Currents
Rise Time Accelerator DC Threshold Voltage
Rise Time Accelerator Pull-Up Current
SDAIN, SCLIN, SDA1–2,
SCL1–2 Pins
SDAIN, SCLIN, SDA1–2,
SCL1–2 Pins
SDAIN, SCLIN, SDA1–2,
SCL1–2 Pins (Note 3)
V
CC
= 2.7V, 5.5V
TIMSET1,0 = 01
TIMSET1,0 = 10
TIMSET1,0 = 11
●
●
●
●
ELECTRICAL CHARACTERISTICS
PARAMETER
ENABLE Falling Threshold Voltage
ENABLE Threshold Hysteresis Voltage
ENABLE Delay, On-Off
ENABLE Delay, Off-On
ENABLE Input Leakage Current
READY Pin Logic Low Output Voltage
READY Off State Input Leakage Current
CONDITIONS
●
MIN
0.8
TYP
1.0
60
60
20
MAX
1.2
UNITS
V
mV
ns
ns
Power Supply/Start-Up
V
ENABLE
= 0V, 5.5V, V
CC
= 5.5V
I
PULL-UP
= 3mA, V
CC
= 2.7V
V
READY
= 0V, 5.5V, V
CC
= 5.5V
I
ALERT
= 3mA, V
CC
= 2.7V
V
ALERT
= 0V, 5.5V
V
ALERT1–2
= 0V, 5.5V
●
●
●
●
●
●
0.1
0.18
0
0.2
0
0
0.8
1.0
80
±
1
0.4
±
1
0.4
±
1
±
1
1.2
µA
V
µA
V
µA
µA
V
mV
●
Rise Time Accelerators
V
SDA,SCL slew
V
RISE,DC
I
BOOST
0.4
●
0.8
1
V/µs
V
mA
0.7
●
0.8
5.5
4
Stuck Low Timeout Circuitry
V
TIMER(L)
V
TIMER(HYST)
T
TIMER1
T
TIMER2
T
TIMER3
V
OS,BUF
V
OS,UP-BUF
V
OS,DOWN-BUF
V
OL
V
OL
V
IL,MAX
V
THSDA,SCL
I
LEAK
Stuck Low Falling Threshold Voltage
Stuck Low Threshold Hysteresis Voltage
Timeout Time #1
Timeout Time #2
Timeout Time #3
Buffer Offset Voltage
Upstream Buffer Offset Voltage
V
IN,BUFFER
= 0V
Downstream Buffer Offset Voltage
V
IN,BUFFER
= 0V
Output Low Voltage, V
IN,BUFFER
= 0V
Output Low Voltage, V
IN,BUFFER
= 0.2V
Buffer Input Logic Low Voltage
Downstream SDA, SCL Logic Threshold Voltage
Input Leakage Current
SDA, SCL Pins;
V
CC
= 0 to 5.5V;
Buffers Inactive
25
12.5
6.25
25
40
70
60
80
0.4
0.52
80
30
15
7.5
60
80
110
110
140
35
17.5
8.75
100
120
150
160
200
400
320
0.4
0.8
0.52
1.0
0.64
1.2
±5
0.64
V
mV
ms
ms
ms
mV
mV
mV
mV
mV
mV
mV
V
V
µA
Upstream-Downstream Buffers
R
BUS
= 10k, V
CC
= 2.7V, 5.5V (Note 4)
●
V
CC
= 2.7V, R
BUS
= 2.7k (Note 4)
V
CC
= 5.5V, R
BUS
= 2.7k (Note 4)
V
CC
= 2.7V, R
BUS
= 2.7k (Note 4)
V
CC
= 5.5V, R
BUS
= 2.7k (Note 4)
SDA, SCL Pins; I
SINK
= 4mA,
V
CC
= 3V, 5.5V
SDA, SCL Pins; I
SINK
= 500µA,
V
CC
= 2.7V, 5.5V
V
CC
= 2.7V, 5.5V
●
●
●
●
●
●
●
●
●
4305f
3
LTC4305
The
●
denotes specifications which apply over the full specified temperature
range, otherwise specifications are at T
A
= 25°C. V
CC
= 3.3V unless otherwise noted.
SYMBOL
I
2
C Interface
V
ADR(H)
V
ADR(L)
I
ADR(IN, L)
I
ADR(IN, H)
I
ADR,FLOAT
V
SDAIN,SCLIN(TH)
V
SDAIN,SCLIN(HY)
I
SDAIN,SCLIN(OH)
C
IN
V
SDAIN(OL)
I
2
C Interface Timing
f
SCL
t
BUF
t
HD, STA
t
SU, STA
t
SU, STO
t
HD, DATI
t
HD, DATO
t
SU, DAT
t
f
t
SP
Maximum SCL Clock Frequency
Bus Free Time Between Stop/Start Condition
Hold Time After (Repeated) Start Condition
Repeated Start Condition Set-Up Time
Stop Condition Set-Up Time
Data Hold Time Input
Data Hold Time Output
Data Set-Up Time
SCL, SDA Fall Times
Pulse Width of Spikes Suppressed by the
Input Filter
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
20 + 0.1
•
C
BUS
50
150
300
400
0.75
45
–30
–30
–25
600
50
1.3
100
0
0
0
900
100
300
250
kHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ADR0–2 Input High Voltage
ADR0–2 Input Low Voltage
ADR0–2 Logic Low Input Current
ADR0–2 Logic High Input Current
ADR0–2 Allowed Input Current
SDAIN, SCLIN Input Falling Threshold Voltages
SDAIN, SCLIN Hysteresis
SDAIN, SCLIN Input Current
SDA, SCL Input Capacitance
SDAIN Output Low Voltage
SCL, SDA = V
CC
(Note 2)
I
SDA
= 4mA, V
CC
= 2.7V
●
●
●
●
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
µA
µA
µA
V
mV
µA
pF
V
0.75
•
V
CC
0.9
•
V
CC
0.1
•
V
CC
0.25
•
V
CC
–30
30
±5
1.4
–60
60
±13
1.6
30
±
5
6
0.2
10
0.4
1.8
–80
80
ADR0–2 = 0V, V
CC
= 5.5V
ADR0–2 = V
CC
= 5.5V
V
CC
= 2.7V, 5.5V (Note 5)
V
CC
= 5.5V
●
●
●
●
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
Guaranteed by design and not subject to test, unless stated
otherwise in the Conditions.
Note 3:
The boosted pull-up currents are regulated to prevent excessively
fast edges for light loads. See the Typical Performance Characteristics for
rise time as a function of V
CC
and parasitic bus capacitance C
BUS
and for
I
BOOST
as a function of V
CC
and temperature.
Note 4:
When a logic low voltage V
LOW
is forced on one side of the
upstream-downstream buffers, the voltage on the other side is regulated
to a voltage V
LOW2
= V
LOW
+ V
OS
is a positive offset voltage. V
OS,DOWN-BUF
is the offset voltage when the LTC4305 is driving the upstream pin (e.g.,
SDAIN) and V
OS,DOWN-BUF
is the offset voltage when the LTC4305 is
driving the downstream pin (e.g., SDA1). See the Typical Performance
Characteristics for V
OS,UP-BUF
and V
OS,DOWN-BUF
as a function of V
CC
and
bus pull-up current.
Note 5:
When floating, the ADR0–ADR2 pins can tolerate pin leakage
currents up to I
ADR,FLOAT
and still convert the address correctly.
4305f
4
LTC4305
TYPICAL PERFOR A CE CHARACTERISTICS
Buffer Circuitry t
PHL
vs Temperature
120
100
V
CC
= 3.3V
t
PHL
(ns)
V
CC
= 5V
60
40
20
0
–50 –25
RISE TIME (ns)
150
V
CC
= 5V
CURRENT (mA)
80
50
25
75
0
TEMPERATURE (°C)
V
OS,UP-BUF
vs Bus Pull-Up Current
180
160
250
140
120
V
CC
= 3.3V
V
CC
= 5V
200
300
V
OS
(mV)
V
OS
(mV)
100
80
60
40
20
0
0
3
1
2
BUS PULL-UP CURRENT (mA)
4
4305 G04
Downstream R
FET
on Resistance
vs V
CC
and Temperature
45
40
35
V
CC
= 3.3V
25
20
15
10
5
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
2
14
12
I
BOOST
(mA)
30
R
ON
(Ω)
U W
100
4305 G01
(T
A
= 25°C unless otherwise specified.)
Rise Time vs C
BUS
vs V
CC
250
dV = 0.3V • V
CC
TO 0.7V • V
CC
R
BUS
= 10k
V
CC
= 3.3V
I
CC
vs Temperature
6
V
CC
= 5V
5
4
3
2
1
0
–50 –25
UPSTREAM CONNECTED TO CHANNEL 1,
SCL BUS LOW, SDA BUS HIGH
50
25
75
0
TEMPERATURE (°C)
100
125
V
CC
= 3.3V
200
100
50
125
0
0
200
600
800
400
CAPACITANCE, C
BUS
(pF)
1000
4305 G02
4305 G03
V
OS,DOWN-BUF
vs Bus Pull-Up Current
V
CC
= 3.3V
150
V
CC
= 5V
100
50
0
0
1
2
3
BUS PULL-UP CURRENT (mA)
4
4305 G05
I
BOOST
vs Temperature
V
CC
= 5V
10
8
6
V
CC
= 3.3V
4
V
CC
= 5V
0
–50 –25
0
25
50
75
TEMPERATURE (°C)
100
125
4305 G06
4305 G07
4305f
5
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