S i 2 1 0 7 / 0 8 / 0 9 /1 0
S
A T E L L I T E
R
E C E I V E R F O R
DVB-S/DSS
W I T H
Q
UICK
L
OCK
AND
Q
UICK
S
CAN
Features
Single-chip tuner, demodulator,
and LNB controller
DVB-S- and DSS-compliant
QPSK/BPSK demodulation
Integrated step-up dc-dc
converter for LNB power supply
(Si2108/10 only)
Input signal level:
–82 to –10 dBm
Symbol rate range:
1 to 45 MBaud
Automatic acquisition and fade
recovery
Automatic gain control
On-chip blind scan accelerator
with
QuickScan
(Si2109/10 only)
DiSEqC™ 2.2 support
Power, C/N, and BER estimators
I C bus interface
3.3/1.8 V supply, 3.3 V I/O
Pb-free/RoHS-compliant
package
VDD_LNA
REXT
2
Pin Assignments
Si2107/08/09/10
GND
GND
VDD_SYNTH
35
VDD_LO
RFIN2
RFIN1
RFIP2
RFIP1
GND
44 43 42 41 40 39 38 37 36
Applications
Set-top boxes
Digital video recorders
Digital televisions
Satellite PC-TV
SMATV trans-modulators
(Satellite Master Antenna TV)
1
2
3
4
5
6
7
8
9
10
11
12
13
XTAL1
XTAL2
VDD_XTAL
XTOUT
VDD_PLL33
INT/RLK/GPO
TS_ERR
TS_VAL
TS_SYNC
SDA
SCL
TS_DATA[7]
TS_DATA[6]
GND
34
33
32
ADDR
VDD_MIX
VDD_BB
VDD_ADC
VSEN/TDET
LNB1/TGEN
ISEN
Top
View
GND
14 15 16 17 18 19 20 21 22
VDD_DIG33
TS_DATA[0]
TS_DATA[1]
TS_DATA[2]
TS_DATA[3]
VDD_DIG33
TS_CLK
TS_DATA[4]
TS_DATA[5]
31
30
29
28
27
26
25
24
23
Description
The Si2107/08/09/10 are a family of pin-compatible, complete front-end solutions
for DSS and DVB-S digital satellite reception. The IC family incorporates a tuner,
demodulator, and LNB controller into a single device resulting in significantly
reduced board space and external component count. The device supports symbol
rates of 1 to 45 MBaud over a 950 to 2150 MHz range. A full suite of features
including automatic acquisition, fade recovery, blind scanning, performance
monitoring, and DiSEqC Level 2.2 compliant signaling are supported. The Si2108/
10 further add short circuit protection, overcurrent protection, and a step-up dc-dc
controller to implement a low-cost LNB supply solution. Si2109/10 versions
include a hardware channel scan accelerator for fast “blindscan”. The Si2107/08/
09/10 family features new channel detection and acquisition technology:
QuickLock
for Si2107/08/09/10 and
QuickScan
for Si2109/10.
QuickLock
achieves fast channel acquisition and
QuickScan,
fast channel detection. An I
2
C
bus interface is used to configure and monitor all internal parameters.
LNB2/DRC
RESET
PWM/DCS
VDD_DIG18
Functional Block Diagram
AGC
Acquisition Control
A/D Converter
De-interleaver
Descrambler
RFIP
Tuner
Demodulator
Viterbi
Decoder
RS
Decoder
TS_CLK
TS_DATA[7:0]
TS_VAL
TS_SYNC
TS_ERR
VSEN/TDET
LNB2/DRC
ISEN/NC
LNB1/TGEN
PWM/DCS
LNB Control
RF Sythesizer
I
2
C Interface
MPEG-TS
INT/RLK/GPO
XOUT
SCL
SDA
Preliminary Rev. 0.81 6/06
Copyright © 2006 by Silicon Laboratories
Si2107/08/09/10
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si2107/08/09/10
2
Preliminary Rev. 0.81
Si2107/08/09/10
T
A B L E O F
C
O N T E N TS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Part Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1. Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2. Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.3. DVB-S/DSS Channel Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4. On-Chip Blindscan Controller: QuickScan (Si2109/10 Only) . . . . . . . . . . . . . . . . . . 21
5.5. LNB Signaling Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6. On-Chip LNB DC-DC Step-Up Controller (Si2108/10 Only) . . . . . . . . . . . . . . . . . . . 21
5.7. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6. Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1. System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3. Receiver Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.4. Tuning Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6.5. Channel Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.6. Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7. LNB Signaling Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.8. On-Chip LNB DC-DC Step-Up Controller (Si2108/10 Only) . . . . . . . . . . . . . . . . . . . 32
6.9. On-Chip Blindscan Controller: QuickScan (Si2109/10 Only) . . . . . . . . . . . . . . . . . . 32
2
C Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7. I
8. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10. Ordering Guide1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11. Package Outline: 44-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
12. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Preliminary Rev. 0.81
3
Si2107/08/09/10
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient temperature
DC supply voltage, 3.3 V
DC supply voltage, 1.8 V
Symbol
T
A
V
3.3
V
1.8
Min
0
3.0
1.71
Typ
—
3.3
1.8
Max
70
3.6
1.89
Unit
°C
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Table 2. Absolute Maximum Ratings
1, 2
Parameter
DC supply voltage, 3.3 V
DC supply voltage, 1.8 V
Input voltage (pins 2, 3, 7, 9, 11_
Input current (pins 2, 3, 7, 9, 11)
Operating ambient temperature
Storage temperature
RF input level
ESD protection (pins 1–44)
Symbol
V
3.3
V
1.8
V
IN
I
IN
T
OP
T
STG
Min
–0.3
–0.3
–0.3
–10
–10
–55
—
—
Max
3.9
2.19
V
3.3
+ 0.3
+10
+70
150
10
2
Unit
V
V
V
mA
°C
°C
dBm
kV
Notes:
1.
Permanent damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operations sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2.
The Si2107/08/09/10 is a high-performance RF integrated circuit. Handling and assembly of these devices should
only be done at ESD-protected workstations.
4
Preliminary Rev. 0.81
Si2107/08/09/10
Table 3. DC Characteristics
(V
3.3
= 3.3 V ±10%, V
1.8
= 1.8 V ±10%, T
A
= 0–70 ºC)
Parameter
Supply Current, 3.3 V
Supply Current, 1.8 V
Input high voltage
Input low voltage
Input leakage
2
Symbol
I
3.3
I
1.8
V
IH
V
IL
I
I
Test Condition
45 Mbaud, CR 7/8
1
20 Mbaud, CR 2/3
1
45 Mbaud, CR 7/8
1
20 Mbaud, CR 2/3
1
Min
—
—
—
—
2.3
0
—
Typ
313
298
292
217
—
—
—
Max
—
—
—
—
5.5
0.8
±10
Unit
mA
mA
mA
mA
V
V
µA
SCL(25), SDA(26)
SCL(25), SDA(26)
SCL(25), SDA(26),
RESET(11),
XTAL1(35), VSEN/
TDET(7)
Output high voltage
Output low voltage
Output leakage
V
OH
V
OL
I
OL
2.4
—
—
—
—
—
—
0.4
±10
V
V
µA
Notes:
1.
LNB dc-dc converter disabled; LNB_EN (CEh[2]) = 0.
2.
ISEN(9) is not tested for leakage current.
Table 4. RF Electrical Characteristics
Parameter
Input power, single channel
Aggregate input power
Input impedance, balanced
Return Loss
Dynamic voltage gain range
Maximum voltage gain
Noise figure
IP3
LO leakage
LO SSB phase noise
LO DSB phase noise (integrated)
RF synthesizer spurious
LO oscillator settling time
t
s,LO
∆
GV
G
V(max)
NF
IP3
3
L
LO
N
LO
N
LO
Max gain
2
Min gain
2
950 to 2150 MHz
100 kHz offset
1 MHz offset
10 kHz to 1/2 Baud
Rate
At 20 MHz offset
Symbol
P
i,ch
P
i,agg
Z
in
Z
SOURCE
= 75
Ω
Test Condition
Min
—
—
—
—
—
—
—
+5
—
—
—
—
—
—
Typ
–82
1
—
75
–10
75
55
+9.5
+15
—
–97
–97
2.1
–40
100
Max
–10
–7
—
—
—
—
+12.5
—
–70
–94
–94
2.8
—
—
Unit
dBm
dBm
Ω
dB
dB
dB
dB
dBm
dBm
dBc/Hz
dBc/Hz
°rms
dBc/Hz
µs
Notes:
1.
For a single channel with SR = 27.5 Mbaud, CR = 7/8, and no added noise. Input power range over which bit error rate
is less than 2e-4 after Viterbi decoder.
2.
Max gain = 0hFFFF in AGC settings registers (25h–26h).
Min gain = 0h0000 in AGC settings registers (25h–26h).
3.
IM3 can be calculated as follows: IM3 = 2 x (IP3 – P
in
).
Preliminary Rev. 0.81
5
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