S i 3 2 2 0 /2 5
D
U A L
P
R O
SLIC
®
P
R O G R A M M A B L E
C M O S S L I C / C
O D E C
Features
Performs all BORSCHT functions
Ideal for applications up to 18 kft
Internal balanced ringing to 65 V
rms
(Si3220)
External bulk ringer support (Si3225)
Software-programmable parameters:
Ringing frequency, amplitude, cadence,
and waveshape (Si3220)
Two-wire ac impedance
Transhybrid balance
DC current loop feed (18–45 mA)
Loop closure and ring trip thresholds
Ground key detect threshold
Automatic switching of up to three battery
supplies
On-hook transmission
Loop or ground start operation with
smooth/abrupt polarity reversal
Modem/fax tone detection
DTMF generation/decoding
Dual tone generators
A-Law/µ-Law, linear PCM
companding
PCM and SPI bus digital interfaces
with programmable interrupts
GCI mode support
3.3 or 5 V operation
GR-909 loop diagnostics
Audio diagnostics with loopback
12 kHz/16 kHz pulse metering
(Si3220)
FSK caller ID generation
Lead-free/RoHS-compliant
Part Number
Si3220
Si3225
Ringing
Method
Internal
External
Ringer
Applications
Digital loop carriers
Central Office telephony
Pair gain remote terminals
Wireless local loop
Private Branch Exchange (PBX) systems
Cable telephony
Voice over IP/voice over DSL
ISDN terminal adapters
Ordering Information
See “Dual ProSLIC Selection
Guide” on page 109.
U.S. Patent #6,567,521
U.S. Patent #6,812,744
Other patents pending
Description
The Dual ProSLIC
®
is a series of low-voltage CMOS devices that integrate both
SLIC and codec functionality into a single IC to provide a complete dual-channel
analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI
specifications. The Si3220 includes internal ringing generation to eliminate
centralized ringers and ringing relays, and the Si3225 supports centralized ringing
for long loop and legacy applications. On-chip subscriber loop and audio testing
allows remote diagnostics and fault detection with no external test equipment or
relays. The Si3220 and Si3225 operate from a single 3.3 or 5 V supply and
interface to standard PCM/SPI or GCI bus digital interfaces. The Si3200 linefeed
interface IC performs all high-voltage functions and operates from a 3.3 V or 5 V
supply as well as single or dual battery supplies up to 100 V. The Si3220 and
Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200 is
available in a thermally-enhanced 16-pin small outline (SOIC) package.
Functional Block Diagram
INT RESET
Si3220/25
CS
SCLK
SDO
SDI
SPI
Control
Interface
Pulse Metering
Subscriber Line
Diagnostics
Ringing
Generator
& Ring Trip
Sense
Dual Tone
Generators
Modem Tone
Detection
2-Wire AC
Impedance
Hybrid Balance
DTMF Decode
FSK
text
Caller ID
Codec A
SLIC A
Linefeed
Control
DAC
ADC
Codec B
TIP
Linefeed
Interface
Channel A
RING
Linefeed
Monitor
DTX
DRX
FSYNC
PCM /
GCI
Interface
DSP
SLIC B
Linefeed
Control
Gain Adjust
Loop Closure,
& Ground Key
Detection
Relay Drivers
DAC
ADC
TIP
Linefeed
Interface
Channel B
RING
PCLK
PLL
Programmable
Audio Filters
Linefeed
Monitor
Rev. 1.2 2/06
Copyright © 2006 by Silicon Laboratories
Si3220/25
Si3220/25
T
A B L E O F
C
O N T E N TS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1. Dual ProSLIC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4. Adaptive Linefeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5. Ground Start Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6. Linefeed Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.7. Loop Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.8. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.9. Automatic Dual Battery Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.10. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.11. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.12. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.13. Internal Unbalanced Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.14. Ringing Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.15. Ring Trip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.16. Relay Driver Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3.17. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.18. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.19. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.20. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.21. Caller ID Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.22. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.23. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.24. Modem Tone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.25. Audio Path Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.26. System Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.27. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
3.28. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.29. PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.30. PCM Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.31. General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.32. System Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4. Pin Descriptions: Si3220/25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5. Pin Descriptions: Si3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
7. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8. Silicon Labs Si3220/25 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
9. Dual ProSLIC Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Rev. 1.2
3
Si3220/25
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information
1
Parameter
Supply Voltage, Si3200 and Si3220/Si3225
High Battery Supply Voltage, Si3200
2
Low Battery Supply Voltage, Si3200
TIP or RING Voltage, Si3205
Symbol
V
DD
, V
DD1
–V
DD4
V
BATH
V
BAT
,V
BATL
V
TIP
,V
RING
Test
Condition
Continuous
10 ms
Continuous
Continuous
Pulse < 10 µs
Pulse < 4 µs
Value
–0.5 to 6.0
0.4 to –104
0.4 to –109
V
BATH
Unit
V
V
V
TIP, RING Current, Si3200
STIPAC, STIPDC, SRINGAC, SRINGDC Current,
Si3220/Si3225
Input Current, Digital Input Pins
Si3220/25 Analog Ground Differential Voltage
(GND1 to ePad, GND2 to ePad, or GND1 to GND2)
3
Si3220/25 Digital Ground Differential Voltage (GND3
to GND4)
3
Si3220/25 Analog to Digital Ground Differential Volt-
age (GND1/GND2/ePad to GND3/GND4)
3
Digital Input Voltage
Operating Temperature Range
Storage Temperature Range
Si3220/Si3225 Thermal Resistance,
Typical
3
(TQFP-64 ePad)
Si3200 Thermal Resistance, Typical
4
(SOIC-16 ePad)
Continuous Power Dissipation, Si3200
5
Continuous Power Dissipation, Si3220/25
I
TIP
, I
RING
–104
V
BATH
–15
V
BATH
–35
±100
±20
±10
±50
±50
±200
mA
mA
mA
mV
mV
mV
I
IN
∆V
GNDA
∆V
GNDD
∆V
GND,A–D
V
IND
T
A
T
STG
θ
JA
θ
JA
P
D
P
D
Continuous
–0.3 to (
V
DDD
+ 0.3)
V
–40 to 100
°C
–40 to 150
°C
25
°C/W
55
T
A
= 85 °C,
SOIC-16
T
A
= 85 °C,
TQFP-64
1
1.6
°C/W
W
W
Notes:
1.
Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2.
The dv/dt of the voltage applied to the V
BAT
, V
BATH
, and V
BATL
pins must be limited to 10 V/µs.
3.
The PCB pad placed under the device package must be connected with multiple vias to the PCB ground layer and to the
GND1-GND4 pins via short traces. The TQFP-64 e-Pad must be properly soldered to the PCB pad during PCB
assembly. This type of low-impedance grounding arrangement is necessary to ensure that maximum differentials are not
exceeded under any operating condition in addition to providing thermal dissipation.
4.
The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper
surface and a large internal copper ground plane. Refer to “AN55: Dual ProSLIC
®
User Guide” or to the Si3220/3225
evaluation board data sheet for specific layout examples.
5.
On-chip thermal limiting circuitry will shut down the circuit at a junction temperature of approximately 150 °C. For optimal
reliability, junction temperatures above 140 °C should be avoided.
4
Rev. 1.2
Si3220/25
Table 2. Recommended Operating Conditions
Parameter
Ambient Temperature
Ambient Temperature
Supply Voltage, Si3220/Si3225
Supply Voltage, Si3200
High Battery Supply Voltage, Si3200
Low Battery Supply Voltage, Si3200
Symbol
T
A
T
A
V
DD1
–V
DD4
V
DD
V
BATH
V
BATL
Test
Condition
K/F-Grade
B/G-Grade
Min*
0
–40
3.13
3.13
–15
–15
Typ
25
25
3.3/5.0
3.3/5.0
—
—
Max*
70
85
5.25
5.25
–99
V
BATH
Unit
o
C
o
C
V
V
V
V
*Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
Table 3. 3.3 V Power Supply Characteristics
1
(V
DD
, V
DD1
– V
DD4
=
3.3 V, T
A
=
0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
V
DD1
–V
DD4
Supply
Current (Si3220/
Si3225)
Symbol
I
VDD1
–I
VDD4
Test Condition
Sleep mode, RESET = 0
Open (high-impedance)
Active on-hook standby
Forward/reverse active off-hook
Min
—
—
—
—
Typ
200
17
16
45 + I
LIM
+ ABIAS
47
26
Max
—
—
—
—
Unit
µA
mA
mA
mA
Forward/reverse active OHT
OBIAS = 4 mA, V
BAT
= –70 V
Ringing, V
RING
= 45 V
rms
, V
BAT
= –70 V,
Sine Wave, 1 REN load
2
—
—
—
—
mA
mA
Notes:
1.
All specifications are for a single channel based on measurements with both channels in the same operating state.
2.
See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating
conditions.
3.
Power consumption does not include additional power required for dc loop feed. Total system power consumption must
include an additional (V
DD
+ |V
BAT
|) x I
LOOP
term.
Rev. 1.2
5
NXP MCU
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