Si5325
P
R E L I M I N A R Y
D
A TA
S
H E E T
µP-P
R O G R A M M A B L E
P
R E C I S I O N
C
L O C K
M
U L T I P L I E R
Description
The Si5325 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5325 accepts dual clock inputs ranging
from 10 to 710 MHz and generates two clock outputs ranging
from 10 to 945 MHz and select frequencies to 1.4 GHz. The
two outputs are divided down separately from a common
source. The device provides virtually any frequency
translation combination across this operating range. The
Si5325 input clock frequency and clock multiplication ratio
are programmable through an I
2
C or SPI interface. The
Si5325 is based on Silicon Laboratories' 3rd-generation
DSPLL
®
technology, which provides any-rate frequency
synthesis in a highly integrated PLL solution that eliminates
the need for external VCXO and loop filter components. The
DSPLL loop bandwidth is digitally programmable, providing
jitter performance optimization at the application level.
Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5325
is ideal for providing clock multiplication in high performance
timing applications
.
Features
Generates any frequency from 10 to 945 MHz and
select frequencies to 1.4 GHz from an input
frequency of 10 to 710 MHz
Low jitter clock outputs w/jitter generation as low as
0.6 ps rms (30 kHz–1.3 MHz)
Integrated loop filter with selectable loop bandwidth
(150 kHz to 2 MHz)
Dual clock inputs w/manual or automatically
controlled hitless switching
Dual clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236)
LOS, FOS alarm outputs
Digitally-controlled output phase adjust
I
2
C or SPI programmable
On-chip voltage regulator for 1.8, 2.5, or 3.3 V
±10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
Applications
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Optical modules
Wireless basestations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
CKIN1
÷ N31
÷ NC1
CKOUT1
®
CKIN2
÷ N32
DSPLL
÷ NC2
÷ N2
CKOUT2
Alarms
Signal Detect
Control
VDD (1.8, 2.5, or 3.3 V)
GND
I
2
C/SPI Port
Device Interrupt
Clock Select
Preliminary Rev. 0.26 7/07
Copyright © 2007 by Silicon Laboratories
Si5325
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5325
Table 1. Performance Specifications
(V
DD
= 1.8, 2.5, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
T
A
V
DD
Test Condition
Min
–40
2.97
2.25
1.62
Typ
25
3.3
2.5
1.8
251
Max
85
3.63
2.75
1.98
279
Unit
ºC
V
V
V
mA
Supply Current
I
DD
f
OUT
= 622.08 MHz
Both CKOUTs enabled
LVPECL format output
CKOUT2 disabled
f
OUT
= 19.44 MHz
Both CKOUTs enabled
CMOS format output
CKOUT2 disabled
Tristate/Sleep Mode
—
—
—
217
204
243
234
mA
mA
—
—
10
10
970
1213
194
TBD
—
—
—
—
220
TBD
710
945
1134
1417
mA
mA
MHz
MHz
Input Clock Frequency
(CKIN1, CKIN2)
Output Clock Frequency
(CKOUT1, CKOUT2)
CK
F
CK
OF
Input frequency and clock
multiplication ratio deter-
mined by programming
device PLL dividers. Consult
Silicon Laboratories configu-
ration software DSPLLsim at
www.silabs.com/timing
to
determine PLL divider set-
tings for a given input fre-
quency/clock multiplication
ratio combination.
Input Clocks (CKIN1, CKIN2)
Differential Voltage Swing
Common Mode Voltage
CKN
DPP
CKN
VCM
1.8 V ±10%
2.5 V ±10%
3.3 V ±10%
Rise/Fall Time
Duty Cycle
CKN
TRF
CKN
DC
20–80%
Whichever is less
40
50
Output Clocks (CKOUT1, CKOUT2)
Common Mode
Differential Output Swing
Single Ended Output
Swing
V
OCM
V
OD
V
SE
LVPECL
100
Ω
load
line-to-line
V
DD
– 1.42
1.1
0.5
—
—
—
V
DD
– 1.25
1.9
0.93
V
V
V
0.25
0.9
1.0
1.1
—
—
—
—
—
—
—
1.9
1.4
1.7
1.95
11
60
—
V
PP
V
V
V
ns
%
ns
Note:
For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from
www.silabs.com/timing.
2
Preliminary Rev. 0.26
Si5325
Table 1. Performance Specifications (Continued)
(V
DD
= 1.8, 2.5, or 3.3 V ±10%, T
A
= –40 to 85 ºC)
Parameter
Rise/Fall Time
Duty Cycle
PLL Performance
Jitter Generation
Symbol
CKO
TRF
CKO
DC
J
GEN
Test Condition
20–80%
Min
—
45
Typ
230
—
0.6
Max
350
55
TBD
Unit
ps
%
ps rms
f
OUT
= 622.08 MHz,
LVPECL output format
50 kHz–80 MHz
12 kHz–20 MHz
800 Hz–80 MHz
—
—
—
—
—
—
—
—
—
—
—
0.6
TBD
0.05
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps rms
ps rms
dB
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
dBc
Jitter Transfer
Phase Noise
J
PK
CKO
PN
f
OUT
= 622.08 MHz
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
Subharmonic Noise
Spurious Noise
Package
Thermal Resistance
Junction to Ambient
SP
SUBH
SP
SPUR
Phase Noise @ 100 kHz Off-
set
Max spur @ n x F3
(n > 1, n x F3 < 100 MHz)
Still Air
θ
JA
—
38
—
ºC/W
Note:
For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from
www.silabs.com/timing.
Table 2. Absolute Maximum Ratings
Parameter
DC Supply Voltage
LVCMOS Input Voltage
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pF, 1.5 kΩ)
ESD MM Tolerance
Latch-Up Tolerance
Symbol
V
DD
V
DIG
T
JCT
T
STG
Value
–0.5 to 3.6
–0.3 to (V
DD
+ 0.3)
–55 to 150
–55 to 150
2
200
JESD78 Compliant
Unit
V
V
C
C
kV
V
Note:
Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.26
3
Si5325
C
4
1 µF
System
Power
Supply
C
3
0.1 µF
Ferrite
Bead
C
2
0.1 µF
C
1
0.1 µF
V
DD
= 3.3 V
GND
VDD
130
Ω
130
Ω
CKIN1+
CKIN1–
CKOUT1+
0.1 µF
100
Ω
+
CKOUT1–
0.1 µF
–
Clock Outputs
82
Ω
82
Ω
CKOUT2+
0.1 µF
100
Ω
CKOUT2–
130
Ω
CKIN2+
CKIN2–
0.1 µF
–
+
Input
Clock
Sources*
130
Ω
V
DD
= 3.3 V
Si5325
INT_C1B
C2B
Interrupt/CKIN_1 Invalid Indicator
CKIN_2 Invalid Indicator
82
Ω
82
Ω
Control Mode (L)
Reset
CMODE
RST
A[2:0]
SDA
SCL
Serial Port Address
Serial Data
Serial Clock
I
2
C Interface
*Note:
Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 1. Si5325 Typical Application Circuit (I2C Control Mode)
C
4
1 µF
System
Power
Supply
C
3
0.1 µF
Ferrite
Bead
C
2
0.1 µF
C
1
0.1 µF
V
DD
= 3.3 V
GND
VDD
130
Ω
130
Ω
CKIN1+
CKIN1–
CKOUT1+
0.1 µF
100
Ω
+
CKOUT1–
0.1 µF
–
Clock Outputs
82
Ω
82
Ω
CKOUT2+
0.1 µF
100
Ω
CKOUT2–
130
Ω
CKIN2+
CKIN2–
0.1 µF
–
+
Input
Clock
Sources*
130
Ω
V
DD
= 3.3 V
Si5325
INT_C1B
C2B
Interrupt/CLKIN_1 Invalid Indicator
CLKIN_2 Invalid Indicator
82
Ω
82
Ω
Control Mode (H)
Reset
CMODE
RST
SS
SDO
SDI
SCLK
Slave Select
Serial Data Out
Serial Data In
Serial Clock
SPI Interface
*Note:
Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 2. Si5325 Typical Application Circuit (SPI Control Mode)
4
Preliminary Rev. 0.26
Si5325
1. Functional Description
The Si5325 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5325 accepts dual clock inputs
ranging from 10 to 710 MHz and generates two
independent, synchronous clock outputs ranging from
10 to 945 MHz and select frequencies to 1.4 GHz. The
device provides virtually any frequency translation
combination across this operating range. Independent
dividers are available for each input clock and output
clock, so the Si5325 can accept input clocks at different
frequencies and it can generate output clocks at
different frequencies. The Si5325 input clock frequency
and clock multiplication ratio are programmable through
an I
2
C or SPI interface. Silicon Laboratories offers a
PC-based software utility, DSPLLsim, that can be used
to determine the optimum PLL divider settings for a
given input frequency/clock multiplication ratio
combination that minimizes phase noise and power
consumption. This utility can be downloaded from
www.silabs.com/timing.
The Si5325 is based on Silicon Laboratories' 3rd-
generation DSPLL
®
technology, which provides any-
rate frequency synthesis in a highly integrated PLL
solution that eliminates the need for external VCXO and
loop filter components. The Si5325 PLL loop bandwidth
is digitally programmable and supports a range from
30 kHz to 1.3 MHz. The DSPLLsim software utility can
be used to calculate valid loop bandwidth settings for a
given input clock frequency/clock multiplication ratio.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5325 has two differential clock outputs. The
electrical format of each clock output is independently
programmable to support LVPECL, LVDS, CML, or
CMOS loads. If not required, the second clock output
can be powered down to minimize power consumption.
The phase difference between the selected input clock
and the output clocks is adjustable in 200 ps increments
for system skew control. In addition, the phase of one
output clock may be adjusted in relation to the phase of
the other output clock. The resolution varies from
800 ps to 2.2 ns depending on the PLL divider settings.
Consult the DSPLLsim configuration software to
determine the phase offset resolution for a given input
clock/clock multiplication ratio combination. For system-
level debugging, a bypass mode is available which
drives the output clock directly from the input clock,
bypassing the internal DSPLL. The device is powered
by a single 1.8, 2.5, or 3.3 V supply.
1.1. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for more
detailed information about the Si5325. The FRM can be
downloaded from
www.silabs.com/timing.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. This utility can be downloaded
from
www.silabs.com/timing.
Preliminary Rev. 0.26
5
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