78Q2123/78Q2133 MicroPHY™
10/100BASE-TX Transceiver
Simplifying System Integration
TM
DATA SHEET
DESCRIPTION
The 78Q2123 and 78Q2133, MicroPHY , are the
smallest 10BASE-T/100BASE-TX Fast Ethernet
transceivers in the market. They include integrated
MII, ENDECs, scrambler/descrambler, dual-speed
clock recovery, and full-featured auto-negotiation
functions. The transmitter includes an on-chip pulse-
shaper and a low-power line driver. The receiver has
an adaptive equalizer and a baseline restoration
circuit required for accurate clock and data recovery.
The transceiver interfaces to Category-5 unshielded
twisted pair (Cat-5 UTP) cabling for 100BASE-TX
applications, and Category-3 unshielded twisted pair
(Cat-3 UTP) for 10BASE-T applications. The MDI is
connected to the line media via dual 1:1 isolation
transformers. No external filter is required. Interface
to the MAC is accomplished through an IEEE-802.3
compliant Media Independent Interface (MII). The
78Q2123/78Q2133 are intended to serve the
embedded Ethernet market, tailored specifically to the
needs of game consoles, broadband modems,
printers, set top boxes and audio/visual equipment. It
is designed for low-power consumption and operates
from a single 3.3V supply. The 78Q2123 is rated for
commercial temperature range and the 78Q2133 is
rated for industrial temperature range.
TM
FEATURES
Smallest 10/100 PHY available
10BASE-T/100BASE-TX IEEE-802.3 compliant
TX and RX functions requiring a dual 1:1 isolation
transformer interface to the line
Integrated MII, 10BASE-T/100BASE-TX ENDEC,
100BASE-TX scrambler/descrambler, and
full-featured auto-negotiation function
Full duplex operation capable
Automatic MDI/MDI-X cross over correction
Register-programmable transmit amplitude
Automatic polarity correction during auto-
negotiation and 10BASE-T signal reception
Power-saving and power-down modes including
transmitter disable
2 Programmable LED indicators (Link and
Activity by default)
User programmable Interrupt pin
Packages: 32-QFN (5x5 mm) and 32-TQFN (5x5mm)
Low Power (~290mW)
Single 3.3 V 0.3V Supply
78Q2123 rated for 0°C to 70°C operation
78Q2133 rated for -40°C to 85°C operation
100M
RXC
TXC
RXD
TXD
SMI
Scrambler,
Parallel/Serial
MRZ/NRZI
MLT3 Encoder
TX CLK GEN
Pulse Shaper
and Filter
Auto
MDI-X
Mux
Auto
Tx/Rx
MII
10M
Parallel/Serial,
Manchester Encoder
Rx/Tx
Carrier Sense,
Collision Detect
Manchester Decoder,
Parallel/Serial
MII
Registers
Serial/Parallel
Descrambler,
5B/4B Decoder
10M
CLK
Recovery
100M
Adaptive EQ,
Baseline Wander Correct,
MLT3 Decode, NRZI/NRZ
LEDs
Clock Reference
Link
CLKIN 25MHz
Act
Rev. 2.0
1
78Q2123/78Q2133 Data Sheet
DS_21x3_001
Table of Contents
1
Functional Description ..........................................................................................................................5
1.1 General...........................................................................................................................................5
1.1.1 Power Management............................................................................................................5
1.1.2 Analog Biasing and Supply Regulation................................................................................5
1.1.3 Clock Selection....................................................................................................................5
1.1.4 Transmit Clock Generation..................................................................................................5
1.1.5 Receive Signal Qualification................................................................................................6
1.1.6 Receive Clock Recovery .....................................................................................................6
1.2 100BASE-TX OPERATION...........................................................................................................6
1.2.1 100BASE-TX Transmit........................................................................................................6
1.2.2 100BASE-TX Receive.........................................................................................................6
1.2.3 PCS Bypass Mode (Auto-negotiate must be off).................................................................6
1.3 10BASE-T OPERATION ...............................................................................................................7
1.3.1 10BASE-T Transmit ............................................................................................................7
1.3.2 10BASE-T Receive .............................................................................................................7
1.3.3 Polarity Correction...............................................................................................................7
1.3.4 SQE TEST ..........................................................................................................................7
1.3.5 Natural Loopback ................................................................................................................7
1.3.6 Repeater Mode ...................................................................................................................7
1.4 Auto-Negotiation ............................................................................................................................8
1.5 Media Independent Interface .........................................................................................................9
1.5.1 MII Transmit and Receive Operation...................................................................................9
1.5.2 Station Management Interface ............................................................................................9
1.6 Additional Features ......................................................................................................................10
1.6.1 LED Indicators...................................................................................................................10
1.6.2 Interrupt Pin.......................................................................................................................10
1.6.3 Automatic MDI/ MDI-X Configuration ................................................................................10
Pin Description.....................................................................................................................................11
2.1 Legend..........................................................................................................................................11
2.2 MII (Media Independent Interface) ..............................................................................................11
2.3 Control and Status .......................................................................................................................12
2.4 MDI (Media Dependent Interface) ...............................................................................................12
2.5 Oscillator/Clock............................................................................................................................12
2.6 Power Supply and Ground...........................................................................................................12
2.7 LED Signals (Programmability Is Secondary Requirement) ......................................................13
Register Description ...........................................................................................................................14
3.1 MR0: Control Register .................................................................................................................15
3.2 MR1: Status Register ...................................................................................................................16
3.3 MR2: PHY Identifier Register 1 ...................................................................................................17
3.4 MR3: PHY Identifier Register 2 ...................................................................................................17
3.5 MR4: Auto-Negotiation Advertisement Register .........................................................................17
3.6 MR5: Auto-Negotiation Link Partner Ability Register ................................................................18
3.7 MR6: Auto-Negotiation Expansion Register ...............................................................................18
3.8 MR16: Vendor Specific Register .................................................................................................18
3.9 MR17: Interrupt Control/Status Register .....................................................................................20
3.10 MR18: Diagnostic Register ..........................................................................................................21
3.11 MR19: Transceiver Control.........................................................................................................21
3.12 MR20: Reserved ..........................................................................................................................21
3.13 MR21: Reserved ..........................................................................................................................21
3.14 MR22: Reserved ..........................................................................................................................21
3.15 MR23: LED Configuration Register .............................................................................................22
3.16 MR24: MDI/MDIX Control Register .............................................................................................22
2
3
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DS_21x3_001
4
78Q2123/78Q2133 Data Sheet
5
6
7
Electrical Specifications ......................................................................................................................23
4.1 Absolute Maximum Ratings .........................................................................................................23
4.2 Recommended Operating Conditions .........................................................................................23
4.3 DCCharacteristics .......................................................................................................................23
4.4 Digital I/O Characteristics ............................................................................................................24
4.5 Digital Timing Characteristics ......................................................................................................25
4.5.2 MII Transmit Interface .......................................................................................................25
4.5.3 MII Receive Interface.........................................................................................................26
4.6 MDIO Interface Input Timing........................................................................................................26
4.6.1 MDIO Interface Output Timing ..........................................................................................27
4.6.2 MDIO Interface Output Timing ..........................................................................................28
4.6.3 100BASE-TX System Timing ............................................................................................29
4.6.4 10BASE-T System Timing.................................................................................................29
4.7 Analog Electrical Characteristics .................................................................................................30
4.7.1 100BASE-TX Transmitter..................................................................................................30
4.7.2 100BASE-TX Transmitter (Informative).............................................................................30
4.7.3 100BASE-TX Receiver......................................................................................................30
4.7.4 10BASE-T Transmitter ......................................................................................................31
4.7.5 10BASE-T Transmitter (Informative) .................................................................................31
4.7.6 10BASE-T Receiver ..........................................................................................................31
4.8 Isolation Transformers .................................................................................................................33
4.9 Reference Crystal.........................................................................................................................33
4.9.1 External XTLP Oscillator Characteristics...........................................................................34
Package Pin Designations ..................................................................................................................35
Package Information ............................................................................................................................36
Ordering Information ...........................................................................................................................36
Revision History ...........................................................................................................................................37
3
78Q2123/78Q2133 Data Sheet
DS_21x3_001
Figures
Figure 1: RST Pulse Duration ...........................................................................................................................25
Figure 2: Transmit Inputs to the 78Q2123/78Q2133........................................................................................25
Figure 3: Receive Outputs from the 78Q2123/78Q2133 .................................................................................26
Figure 4: MDIO as an Input to the 78Q2123/78Q2133 ....................................................................................26
Figure 5: MDIO as an Output to the 78Q2123/78Q2133............................................................................. 27
Figure 6: MDIO Interface Output Timing...................................................................................................... 28
Figure 7: Application Diagram for 78Q2123/78Q2133 .....................................................................................32
Figure 8: External XTLP Oscillator Characteristics ...................................................................................... 34
Figure 9: Package Pin Designations.................................................................................................................35
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DS_21x3_001
78Q2123/78Q2133 Data Sheet
1 Functional Description
1.1
1.1.1
General
Power Management
The 78Q2123 and 78Q2133 have three power saving modes:
Chip Power-Down
Receive Power Management
Transmit High Impedance Mode
Chip power-down is activated by setting the PWRDN bit in MII register MR0.11. When the chip is in
power-down mode, all on-chip circuitry is shut off, and the device consumes minimum power. While in
the power-down state, the 78Q2123/78Q2133 still respond to management transactions.
Receive power management (RXCC mode) is activated by setting the RXCC bit in MII register MR16.0.
In this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (PLL), and all other
receive circuitry will be powered down when no valid MLT-3 signal is present at the UTP receive line
interface. As soon as a valid signal is detected, all circuits will automatically be powered up to resume
normal operation. During this mode of operation, RX_CLK will be inactive when there is no data being
received. Note that the RXCC mode is not supported during 10BASE-T operation.
Transmit high impedance mode is activated by setting the TXHIM bit in MII register MR16.12. In this
mode of operation, the transmit UTP drivers are in a high impedance state and TX_CLK is tri-stated. A
weak internal pull-up is enabled on TX_CLK. The receive circuitry remains fully operational. The default
state of MR16.12 is a logic low for disabling the transmit high impedance mode. Only a reset condition will
automatically clear MR16.12. The transmitter is fully functional when MR16.12 is cleared. This feature is
useful when configuring a system for Wake-On LAN (when the 78Q2123/78Q2133 are coupled with a
Wake-On LAN capable MAC).
1.1.2
Analog Biasing and Supply Regulation
The 78Q2123/78Q2133 require no external component to generate on-chip bias voltages and currents.
High accuracy is maintained through a closed-loop trimmed biasing network.
On-chip digital logic runs off an internal voltage regulator. Hence only a single 3.3V ( 0.3V) supply is
required to power-up the device. The on-chip regulator is not affected by the power-down mode.
1.1.3
Clock Selection
The 78Q2123/78Q2133 have an on-chip crystal oscillator which can also be driven by an external oscillator.
In this mode of operation, a 25 MHz crystal should be connected between the XTLP and XTLN pins.
Alternatively, an external 25 MHz clock input can be connected to the XTLP pin. In this mode of operation,
a crystal is not required and the XTLN pin must be tied to ground.
1.1.4
Transmit Clock Generation
The transmitter uses an on-chip frequency synthesizer to generate the transmit clock. In 100BASE-TX
operation, the synthesizer multiplies the reference clock by 5 to obtain the internal 125 MHz serial transmit
clock. In 10BASE-T mode, it generates an internal 20MHz transmit clock by multiplying the reference
25 MHz clock by 4/5. The synthesizer references either the local 25 MHz crystal oscillator, or the externally
applied clock, depending on the selected mode of operation.
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