PSMN019-100YL
4 November 2016
N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56
Product data sheet
1. General description
Logic level N-channel MOSFET in an LFPAK56 (Power SO8) package using TrenchMOS
technology. This product is designed and qualified for use in a wide range of power
supply & motor control equipment.
2. Features and benefits
•
•
•
•
Advanced TrenchMOS provides low R
DSon
and low gate charge
Logic level gate operation
Avalanche rated, 100 % tested
LFPAK provides maximum power density in a Power SO8 package
3. Applications
•
•
•
•
•
Synchronous rectification in power supply equipment
Chargers & adaptors with V
out
< 10 V
Fast charge & USB-PD applications
Battery powered motor control
LED lighting & TV backlight
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
25 °C ≤ T
j
≤ 175 °C
V
GS
= 5 V; T
mb
= 25 °C;
Fig. 2
T
mb
= 25 °C;
Fig. 1
V
GS
= 5 V; I
D
= 15 A; T
j
= 25 °C;
Fig. 11
Min
-
-
-
Typ
-
-
-
Max
100
56
167
Unit
V
A
W
Static characteristics
drain-source on-state
resistance
gate-drain charge
-
14.6
19
mΩ
Dynamic characteristics
Q
GD
I
D
= 15 A; V
DS
= 80 V; V
GS
= 5 V;
T
j
= 25 °C;
Fig. 13; Fig. 14
-
14.1
-
nC
Nexperia
PSMN019-100YL
N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56
5. Pinning information
Table 2.
Pin
1
2
3
4
mb
Pinning information
Symbol Description
S
S
S
G
D
source
source
source
gate
mounting base; connected to
drain
1 2 3 4
G
mbb076
Simplified outline
mb
Graphic symbol
D
S
LFPAK56; Power-
SO8 (SOT669)
6. Ordering information
Table 3.
Ordering information
Package
Name
PSMN019-100YL
LFPAK56;
Power-SO8
Description
Plastic single-ended surface-mounted package
(LFPAK56; Power-SO8); 4 leads
Version
SOT669
Type number
7. Marking
Table 4.
Marking codes
Marking code
19L100
Type number
PSMN019-100YL
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
P
tot
I
D
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
T
mb
= 25 °C;
Fig. 1
V
GS
= 5 V; T
mb
= 25 °C;
Fig. 2
V
GS
= 5 V; T
mb
= 100 °C;
Fig. 2
I
DM
T
stg
PSMN019-100YL
Conditions
25 °C ≤ T
j
≤ 175 °C
R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
Max
100
100
20
167
56
40
226
175
Unit
V
V
V
W
A
A
A
°C
peak drain current
storage temperature
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C;
Fig. 3
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
4 November 2016
2 / 13
Nexperia
PSMN019-100YL
N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56
Symbol
T
j
I
S
I
SM
E
DS(AL)S
Parameter
junction temperature
Conditions
Min
-55
Max
175
Unit
°C
Source-drain diode
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
I
D
= 56 A; V
sup
≤ 100 V; R
GS
= 50 Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped;
Fig. 4
[1]
[2]
120
P
der
(%)
80
-
-
56
226
A
A
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
[1][2]
-
94.1
mJ
Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
Refer to application note AN10273 for further information.
03aa16
I
D
(A)
60
50
40
30
003aai925
40
20
10
0
0
50
100
150
T
mb
(°C)
200
0
0
40
80
120
160
T
mb
(°C)
200
Fig. 1.
Normalized total power dissipation as a
function of mounting base temperature
Fig. 2.
Continuous drain current as a function of
mounting base temperature
PSMN019-100YL
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
4 November 2016
3 / 13
Nexperia
PSMN019-100YL
N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56
I
D
(A)
10
3
003aai927
Limit R
DSon
= V
DS
/ I
D
10
2
t
p
= 10 us
100 us
10
DC
1
1 ms
10 ms
100 ms
10
-1
1
10
10
2
10
3
V
DS
(V)
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
I
AL
(A)
10
2
003aai926
10
(1)
(2)
1
(3)
10
-1
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig. 4.
Avalanche rating; avalanche current as a function of avalanche time
9. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
Conditions
Fig. 5
Min
-
Typ
-
Max
0.9
Unit
K/W
PSMN019-100YL
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
4 November 2016
4 / 13
Nexperia
PSMN019-100YL
N-channel 100 V, 19 mΩ logic level MOSFET in LFPAK56
Z
th(j-mb)
(K/W)
1
δ = 0.5
0.2
003aai928
10
-1
0.1
0.05
0.02
single shot
P
δ=
t
p
T
10
-2
t
p
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
T
t
p
(s)
1
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
=V
GS
; T
j
= 25 °C;
Fig. 9;
Fig. 10
I
D
= 1 mA; V
DS
=V
GS
; T
j
= -55 °C;
Fig. 9
I
D
= 1 mA; V
DS
=V
GS
; T
j
= 175 °C;
Fig. 9
I
DSS
drain leakage current
V
DS
= 100 V; V
GS
= 0 V; T
j
= 175 °C
V
DS
= 100 V; V
GS
= 0 V; T
j
= 25 °C
I
GSS
gate leakage current
V
GS
= 16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -16 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 5 V; I
D
= 15 A; T
j
= 25 °C;
Fig. 11
V
GS
= 10 V; I
D
= 15 A; T
j
= 25 °C;
Fig. 11
V
GS
= 5 V; I
D
= 15 A; T
j
= 175 °C;
Fig. 11; Fig. 12
Dynamic characteristics
Q
G(tot)
total gate charge
I
D
= 15 A; V
DS
= 80 V; V
GS
= 10 V;
T
j
= 25 °C;
Fig. 13; Fig. 14
I
D
= 15 A; V
DS
= 80 V; V
GS
= 5 V;
Q
GS
PSMN019-100YL
Min
100
90
1.4
-
0.5
-
-
-
-
-
-
-
Typ
-
-
1.7
-
-
-
0.04
2
2
14.6
14
-
Max
-
-
2.1
2.45
-
500
10
100
100
19
18
52.4
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Static characteristics
V
GS(th)
-
-
-
72.4
39
8.5
©
-
-
-
nC
nC
nC
5 / 13
gate-source charge
T
j
= 25 °C;
Fig. 13; Fig. 14
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
4 November 2016
NXP MCU
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