LC03-6R2
ESD Protection Diode
Low Capacitance Surface Mount
ESD Protection for High-Speed Data
Interfaces
The LC03−6 surge protection is designed to protect equipment
attached to high speed communication lines from ESD, EFT, and
lighting.
Features
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•
•
•
•
•
SO−8 Package
Peak Power
−
2000 Watts 8 x 20
mS
ITU K.20 I
PP
= 40 A (5/310
ms)
Bellcore 1089 (Intra−Building) 100 A (2/10
ms)
ESD Rating:
IEC 61000−4−2 (ESD) 15 kV (air) 8 kV (contact)
IEC 61000−4−4 (EFT) 40 A (5/50 ns)
IEC 61000−4−5 (lighting) 95 A (8/20
ms)
•
UL Flammability Rating of 94 V−0
•
Pb−Free Package is Available
Typical Applications
SO−8 LOW CAPACITANCE
VOLTAGE SUPPRESSOR
2 kW PEAK POWER
6 VOLTS
PIN CONFIGURATION
AND SCHEMATIC
1
2
3
4
8
7
6
5
•
High Speed Communication Line Protection
MAXIMUM RATINGS
Rating
Peak Power Dissipation
8 x 20
mS
@ T
A
= 25°C (Note 1)
Peak Pulse Current (8 x 20
mS
Waveform)
Junction and Storage Temperature Range
Lead Solder Temperature
−
Maximum 10 Seconds Duration
Symbol
P
pk
I
PP
T
J
, T
stg
T
L
Value
2000
100
−55
to +150
260
Unit
W
A
°C
°C
8
1
SOIC−8
CASE 751
PLASTIC
MARKING DIAGRAM
8
LC036
AYWWG
G
1
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Non−repetitive current pulse 8 x 20
mS
exponential decay waveform
LC036 = Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
LC03−6R2
LC03−6R2G
Package
SO−8
SO−8
(Pb−Free)
Shipping
†
2500/Tape & Reel
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2007
October, 2017
−
Rev. 5
1
Publication Order Number:
LC03−6R2/D
LC03−6R2
ELECTRICAL CHARACTERISTICS
Characteristic
Reverse Breakdown Voltage @ I
t
= 1.0 mA
Reverse Leakage Current @ V
RWN
= 5.0 V
Maximum Clamping Voltage @ I
PP
= 50 A, 8 x 20
mS
Maximum Clamping Voltage @ I
PP
= 100 A, 8 x 20
mS
Between I/O Pins and Ground @ V
R
= 0 V, 1.0 MHz
Between I/O Pins @ V
R
= 0 Volts, 1.0 MHz
Symbol
V
BR
I
R
V
C
V
C
Capacitance
Capacitance
Min
6.8
N/A
N/A
N/A
−
−
Typ
−
−
−
−
16
8.0
Max
−
20
15
20
25
12
Unit
V
mA
V
V
pF
pF
TYPICAL CHARACTERISTICS
10
8
6
4
2
0
−80 −60 −40 −20
0 20 40 60 80 100 120 140
T, TEMPERATURE (°C)
I
R
, REVERSE LEAKAGE (mA)
V
Z
, REVERSE VOLTAGE (V)
16
14
12
10
8
6
4
2
0
−80 −60 −40 −20
0
20
40
60
80 100 120 140
T, TEMPERATURE (°C)
Figure 1. Reverse Voltage versus Temperature
Figure 2. Reverse Leakage versus
Temperature
20
V
C
, CLAMPING VOLTAGE (V)
18
16
14
12
10
8
6
4
2
0
0
10
20
30
40
50
60
70
80
90 100 110
8 x 20
ms
Waveform
100
% OF PEAK PULSE CURRENT
90
80
70
60
50
40
30
20
10
0
0
t
r
PEAK VALUE I
RSM
@ 8
ms
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8
ms
HALF VALUE I
RSM
/2 @ 20
ms
t
P
20
40
t, TIME (ms)
60
80
I
PP
, PEAK PULSE CURRENT (A)
Figure 3. 8 x 20
ms
Pulse Waveform
Figure 4. Clamping Voltage versus Peak Pulse
Current
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2
LC03−6R2
APPLICATIONS INFORMATION
The LC03−6 ON Semiconductor’s device is a surge
protection Diode array designed to protect sensitive
electronics such as communications systems, computers, and
computer peripherals against damage due to transient
overvoltage conditions caused by lightning, electrostatic
discharge (ESD), and electrical fast transients (EFT).
Because of its relative low capacitance (<25 pf), it can be used
in high speed I/O data lines such as USB 1.1 ports.
The integrated design of the LC03−6 device offers high
surge rating, low capacitance steering diodes, and a surge
protection diode integrated in a single package (SO−8). In
addition, this device offers compliance to Bellcore 1089
requirements (intra−building).
LC03−6 Device’s Configurations Options
Protection of Two High−speed I/O Data Lines
If differential protection is required by some particular
applications, then the configuration for differential protection
is made as shown in the Figure 6:
LC03−6
Line 1
In
N/C
N/C
Line 2
In
N/C
N/C
Line 2
Out
Line 1
Out
Figure 6. Configuration for Differential
Protection (Line−to−Line)
T1/E1 Linecard Protection (Intra−Building)
The LC03−6 device is able to protect two high speed data
lines against transient overvoltage conditions by driving
them to a fixed reference point for clamping purposes.
Depending in the application’s requirements, the LC03−6
device can be configured for protection in either differential
mode (Line−to−Line) or common mode (Line−to−ground).
The Figure 5 shows the connection for Differential mode
(Line−to−Line) and Common mode (Line−to−Ground)
protection. The inputs and outputs of the I/O data lines are
connected at terminals 1 to 8, and 4 to 5 while the terminals
2, 3, 6 and 7 are connected to ground; for better performance,
it is recommended to minimize parasitic inductances by
using ground planes and minimizing the PCB trace lengths
for the ground return connections.
LC03−6
Line 1
In
Line 1
Out
The Figure 7 shows a typical schematic for a T1/E1 line
card protection circuit. The LC03−6 device is connected
between Tip and Ring on the transmit and receive line pairs.
it provides protection to metallic and common mode lightning
surges per Bellcore 1089 intra−building (For further
information, see Bellcore 1089 standard). A metallic voltage
is defined as a difference of potential between the T and R
terminals of a telecommunications pair. Currents caused by
lightning, in the absence of protector operation and with
balanced terminal equipment and telecommunications loop,
cause Tip and Ring conductors to attain the same potential
hence do not produce metallic transients. Common mode
surges are suppressed by the isolation of the transformer.
Line 2
In
Line 2
Out
Figure 5. Configuration for Differential
and Common Mode Protection
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3
LC03−6R2
PTC
RTIP
R1
R3
T1
LC03−6
PTC
RRING
T1/E1
TRANSCEIVER
TTIP
R2
R4
LC03−6
T2
PTC
TRING
R5
PTC
Figure 7. Typical T1 Line Card Protection
ESD Protection in USB 1.1 Port Applications
As we know, a USB port is composed of four lines. The
lines D+ and D− are used for bi−directional data
transmission, and the remaining two lines are reserved for
bus voltage and ground. Since USB is a hot plugging and
unplugging system, all its four lines have the risk to receive
ESD conditions in the real field of the application.
Typical ESD protection techniques are commonly formed
by the combination of different discrete semiconductor
products which make this technique obsolete and
non−efficient because the interconnections of the discrete
devices increase the parasitic inductance effects during a
transient condition which reduces significantly the
performance of the ESD protection circuit. The LC03−6
device provides a unique surge protection Diode array
designed to protect two I/O data lines (single USB port)
against damage due to ESD conditions or transient voltage
conditions. Because of its low capacitance, it can be used in
high speed I/O data lines such as USB 1.1 components. In
addition to its low capacitance characteristics, the LC03−6
device from ON Semiconductor complies with the most
common industrial standards for ESD, EFT and surge
protection:
IEC61000−4−2,
IEC61000−4−4,
IEC61000−4−5.
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4
LC03−6R2
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
A
8
5
B
1
S
4
0.25 (0.010)
M
Y
M
−Y−
G
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
_
8
_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
_
8
_
0.010
0.020
0.228
0.244
C
−Z−
H
D
0.25 (0.010)
M
SEATING
PLANE
N
X 45
_
0.10 (0.004)
M
J
Z Y
S
X
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
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