QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1255
16-BIT, 250KSPS ADC
LTC1605CG/LTC1606CG
DESCRIPTION
The LTC1606 is a 250Ksps ADC that draws only
75mW from a single +5V Supply, while the LTC1605
is a 100Ksps ADC that draws only 55mW from a sin-
gle +5V supply. DC1255 can use either part. The fol-
lowing text refers to the LTC1606 but it also applies
to the LTC1605 with appropriate sampling frequency
considerations.
Demonstration circuit 1255 provides the user a
means of evaluating the performance of the
LTC1605/LTC1606 and is intended to demonstrate
recommended grounding, part placement, routing
and bypassing.
Design files for this circuit board are available. Call
the LTC factory.
LTC is a trademark of Linear Technology Corporation
Figure1. Connection Diagram
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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1255
16-BIT, 250KSPS ADC
DC718B QUICK START PROCEDURE
Connect DC1255A to a DC718B USB High Speed Data
Collection Board using connector J2. Connect DC718B
to a host PC with a standard USB A/B cable. Apply 7V-
9V DC to the 7V-9V and GND terminals. Apply +15V
and -15V to the indicated terminals, if the internal
buffer is to be used (default). Apply a low jitter signal
source to J1. As a clock source, either the onboard
clock or a low jitter 250kHz 10dBm sine wave or
square wave to connector J3 can be used. Note that J3
has a 50• termination resistor to ground. Run the
QuickEval-II software (Pscope.exe version K51 or later)
supplied with DC718B or download it from
www.linear.com.
Complete software documentation is available from the
Help menu. Updates can be downloaded from the Tools
menu. Check for updates periodically as new features
may be added.
The Pscope software should recognize DC1255A and
configure itself automatically.
Click the Collect button (See Figure 2) to begin acquiring
data. Depending on which board was previously used by
Pscope, it may be necessary to press Collect a second
time. The Collect button then changes to Pause, which
can be clicked to stop data acquisition.
DC1255 SETUP
DC Power
DC1255 requires 7-9VDC at approximately 24mA and
+/- 15V to power amplifier U3. If you do not use U3
(see jumper JP1) you do not have to provide +/-15V. The 7-9VDC
supply powers the ADC through a LT1761-5 regulator
witch provides protection against accidental reverse
bias. See Figure 1 for connection details.
Clock Source
JP10 (CLK) determines whether DC1255 is inter-
nally (default) or externally clocked. The internal
clock consists of an ECS 1MHz clock oscillator,
which is divided by a 74VHC161 counter. This oscil-
lator can be turned off by setting JP9 (OSCEN) to
the OFF position. Jumpers (JP4-JP7) set the inter-
nal clock divider ratio for the appropriate ADC
(LTC1605 or LTC1606). See the table in Figure 1
for jumper settings.
For an external clock, you must provide a low jitter
10dBm sine or square wave to J3. Note that J3 has a
50• termination resistor to ground. Driving this input
with logic will be difficult. Slow rising edges may
compromise SNR of the converter in the presence of
high-amplitude higher frequency input signals. The
demo board incorporates an edge detector circuit in
the form of an inverter (U14) followed by a 200nsec
delay, feeding, along with the original clock source, a
two input NAND gate (U7B). This will generate an ap-
proximate 200nsec active low pulse at the ADC if the
clock high time is greater than 200nsec. A 50% duty
cycle clock at 250kHz is typically used to test these
demo boards. Shorter duty cycle pulses (active High
at J3) can be used to a minimum of 40nsec.
Data Output
Parallel data output from this board (0V-3.3V), if not
connected to DC718, can be acquired by a logic ana-
lyzer, and subsequently imported into a spreadsheet,
or mathematical package depending on what form of
digital signal processing is desired.
CS#
BYTE and CS# Jumpers
The demo board is typically shipped with BYTE (JP3)
and CS# (JP8) tied to ground. If you intend to operate
this device in a fashion that involves these lines, you
can use the jumpers as a means of introducing these
signals from an external source.
R eference
JP2
allows you to select an on chip reference or an
external LT1019A-2.5 (default) as the reference. The
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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1255
16-BIT, 250KSPS ADC
typical drift specifications of the external reference
are similar to the on chip reference, but the LT1019-
2.5 has guaranteed maximums.
Analog Input
The demo board is shipped with
JP1
in the ‘‘IN’’ posi-
tion, in which case, the input amplifier is in the signal
path. With
JP1
in the ‘‘IN’’ position, U3 (LT1468) pro-
vides a gain of 9dB. This will allow a signal generator,
with a 2.5V RMS output level to drive the converter to
full scale. This amplifier does not compromise the
SNR or distortion performance of the converter. The
input noise density of the LT1468 itself is 5nV/•Hz.
In the circuit as configured, the feedback network im-
pedance and the amplifier’s input noise current con-
tribute noise power; to produce an input referred
noise density of 7.44nV/•Hz. With a gain of 2.82, this
produces 17uV RMS of noise in the 675kHz band-
width imposed by the converter. This is a signal to
noise ratio of 112dB at full scale. This is of course not
verifiable at the output of the ADC.
With JP1 in the ‘‘OUT’’ position, the input impedance
at J1 is 10K•. With JP1 in the ‘‘IN’’ position, the input
impedance is very high.
If J1 is driven by a generator intended to drive a 50•
impedance, you may want to use a 50• through-
terminator. If a higher impedance source is to be
evaluated, you will see better results with the ampli-
fier in the signal path.
If you want to evaluate the amplifier in unity gain, re-
move R5, or solder a low value resistor in parallel
with R16. If you want to evaluate the amplifier with
higher gain, you may reduce the value of R5. If you
use very high quality resistors, you should be able to
increase the gain to 50 before the noise floor of the
converter rises discernibly. A voltage gain of 10
should result in the typical SNR of 90dB dropping to
89.9dB. A voltage gain of 50 should give approx
88.7dB, and a gain of 100 would give approximately
86dB SNR. THD will increase but with a gain of 50,
the THD of the LT1468 is still typically in the range of
-90dB.
If the amplifier is configured for high gain, ground
potential differences between the various instruments
on your bench top may be found to develop a differ-
ential component at the input to the demo board.
Transformer isolation may be required to produce
good results with a gain of 50.
Data Col
Data Co llection
The system used for data collection may have a
negative effect on how well the demo board performs,
if it produces significant ground current through the
demo board.
This demo board is tested in house by duplicating the
FFT plot shown in the lower left of page 6 of the
LTC1606 data sheet. This involves using a low jitter,
250kHz clock source for the encode clock, along with
a low noise, low distortion sinusoidal generator at a
frequency in the neighborhood of 1KHz. The amplifier
is ‘‘IN’’ for in house test, and the input signal level is
approx -1dBfs. The FFT shown in the data sheet is a
4096-point FFT, with the input frequency at precisely
1037.5976Hz. This frequency is ‘‘coherent’’ (produces
an integral number of cycles of the fundamental
within the window) for a 250kHz clock frequency, and
a prime number of cycles (17 cycles). A prime num-
ber of integral cycles exercises the greatest number
of possible input codes. Other clock rates require dif-
ferent input frequencies for coherent sampling. To
calculate the input frequency
f
i
, for a given sampling
frequency
f
s
, number of samples
n
and prime integer
m
, use the following formula.
There are a number of scenarios that can produce
misleading results when evaluating an ADC. One that
fi
=
m
*
fs
n
is common is feeding the converter with a frequency,
that is a sub-multiple of the sample rate, and which
will only exercise a small subset of the possible out-
put codes.
Also, note that DC1255 does not have an anti-aliasing
filter. Following jumper JP1, is an 800kHz first order
low pass filter (R1 and C2).
This does not appreciably change the --3dB point of
-
the converter, which is typically 675kHz. Hence, R1
and C2 do not constitute an anti-aliasing filter. If you
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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1255
16-BIT, 250KSPS ADC
require an anti-aliasing filter in your evaluation, it
should generally be placed prior to the LT1468 or any
external amplifier in the signal path. If you have fre-
quency components that are above Nyquist (1/2
f
s
),
and up to and beyond 675KHz they will fold back into
the DC-125KHz base band, and become indistin-
guishable from signals in this band.
If you do not have a signal generator capable of ppm
levels of frequency accuracy, you can use an FFT with
windowing to reduce the ‘‘leakage’’ or spreading of
the fundamental, to get a close approximation of the
performance parameters. If an amplifier or clock
source with poor phase noise is used, the windowing
will not improve the SNR.
The signal source typically used for in house testing
is a B&K 1051. The internal clock source is adequate
for most applications. As with any high performance
ADC, this part is sensitive to layout. The area immedi-
ately surrounding the ADC should be used as a guide-
line for placement, and routing of the various compo-
nents associated with the ADC. Note should also be
taken of the ground plane used in the layout of this
board.
Figure 2. DC1255 FastDAACS Screenshot
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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1255
16-BIT, 250KSPS ADC
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