PD - 96893C
IRFB3207
IRFS3207
IRFSL3207
Applications
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
Benefits
l
Worldwide Best R
DS(on)
in TO-220
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
G
S
HEXFET
®
Power MOSFET
D
V
DSS
R
DS(on)
typ.
max.
I
D
4.5m
:
180A
75V
3.6m
:
GDS
TO-220AB
IRFB3207
GDS
D
2
Pak
IRFS3207
GDS
TO-262
IRFSL3207
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
C
= 25°C
V
GS
dV/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
d
130
180
720
330
2.2
± 20
5.8
-55 to + 175
300
10lb in (1.1N m)
Max.
Units
A
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
W
W/°C
V
V/ns
°C
f
x
x
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
Avalanche Current
Ã
e
910
See Fig. 14, 15, 16a, 16b,
mJ
A
mJ
Repetitive Avalanche Energy
g
Thermal Resistance
Symbol
R
θJC
R
θCS
R
θJA
R
θJA
Junction-to-Case
k
Parameter
Typ.
–––
0.50
–––
–––
Max.
0.45
–––
62
40
Units
°C/W
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220
k
Junction-to-Ambient (PCB Mount) , D Pak
2
jk
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1
03/06/06
IRF/B/S/SL3207
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
R
DS(on)
V
GS(th)
I
DSS
I
GSS
R
G
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Input Resistance
Min. Typ. Max. Units
75
–––
–––
2.0
–––
–––
–––
–––
–––
––– –––
0.069 –––
3.6
4.5
–––
4.0
–––
20
––– 250
––– 200
––– -200
1.2
–––
Conditions
V V
GS
= 0V, I
D
= 250µA
V/°C Reference to 25°C, I
D
= 1mA
mΩ V
GS
= 10V, I
D
= 75A
V V
DS
= V
GS
, I
D
= 250µA
µA V
DS
= 75V, V
GS
= 0V
V
DS
= 75V, V
GS
= 0V, T
J
= 125°C
nA V
GS
= 20V
V
GS
= -20V
Ω
f = 1MHz, open drain
g
d
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
eff. (ER)
C
oss
eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
–––
180
48
68
29
120
68
74
7600
710
390
920
1010
–––
260
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
Conditions
V
DS
= 50V, I
D
= 75A
I
D
= 75A
V
DS
= 60V
V
GS
= 10V
V
DD
= 48V
I
D
= 75A
R
G
= 2.6Ω
V
GS
= 10V
V
GS
= 0V
V
DS
= 50V
ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 60V
V
GS
= 0V, V
DS
= 0V to 60V
150
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Effective Output Capacitance (Energy Related) –––
–––
Effective Output Capacitance (Time Related)
g
g
ns
pF
h
j
, See Fig.11
h
, See Fig. 5
D
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
––– 180
–––
Conditions
MOSFET symbol
showing the
integral reverse
G
S
A
Ãdi
720
––– –––
1.3
V
–––
42
63
ns
–––
49
74
–––
65
98
nC
–––
92
140
–––
2.6
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode.
T
J
= 25°C, I
S
= 75A, V
GS
= 0V
T
J
= 25°C
V
R
= 64V,
T
J
= 125°C
I
F
= 75A
di/dt = 100A/µs
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
g
g
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.33mH
R
G
= 25Ω, I
AS
= 75A, V
GS
=10V. Part not recommended for use
above this value.
I
SD
≤
75A, di/dt
≤
500A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C
2
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IRF/B/S/SL3207
1000
TOP
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
BOTTOM
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
100
10
4.5V
≤
60µs PULSE WIDTH
Tj = 175°C
10
0.1
1
10
100
4.5V
1
0.1
1
≤
60µs PULSE WIDTH
Tj = 25°C
10
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000.0
2.5
Fig 2.
Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 75A
VGS = 10V
2.0
ID, Drain-to-Source Current
(Α)
TJ = 175°C
100.0
TJ = 25°C
1.5
10.0
1.0
VDS = 50V
1.0
4.0
5.0
6.0
7.0
≤
60µs PULSE WIDTH
8.0
9.0
0.5
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
12000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
8000
Fig 4.
Normalized On-Resistance vs. Temperature
20
VGS, Gate-to-Source Voltage (V)
ID= 75A
16
10000
VDS = 60V
VDS= 38V
C, Capacitance (pF)
Ciss
12
6000
8
4000
4
2000
Coss
Crss
1
10
100
0
0
0
40
80
120
160
200
240
280
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRF/B/S/SL3207
1000.0
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
100.0
TJ = 175°C
100
100µsec
10.0
10
1.0
TJ = 25°C
1
VGS = 0V
0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Tc = 25°C
Tj = 175°C
Single Pulse
1
10
1msec
10msec
DC
100
1000
0.1
VSD, Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage
200
LIMITED BY PACKAGE
100
Fig 8.
Maximum Safe Operating Area
ID , Drain Current (A)
150
90
100
80
50
0
25
50
75
100
125
150
175
TC , Case Temperature (°C)
70
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 9.
Maximum Drain Current vs.
Case Temperature
EAS, Single Pulse Avalanche Energy (mJ)
3.0
Fig 10.
Drain-to-Source Breakdown Voltage
4000
2.5
3000
I D
TOP
12A
16A
BOTTOM
75A
2.0
Energy (µJ)
1.5
2000
1.0
1000
0.5
0.0
20
30
40
50
60
70
80
0
25
50
75
100
125
150
175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (°C)
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy Vs. DrainCurrent
4
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IRF/B/S/SL3207
1
D = 0.50
Thermal Response ( ZthJC )
0.1
0.20
0.10
0.05
τ
J
R
1
R
1
τ
J
τ
1
τ
2
R
2
R
2
τ
C
τ
1
τ
2
τ
0.01
0.02
0.01
Ri (°C/W)
τi
(sec)
0.2151 0.001175
0.2350
0.017994
0.001
Ci=
τi/Ri
Ci= i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
0.0001
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
Avalanche Current (A)
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆
Tj = 150°C and
Tstart =25°C (Single Pulse)
0.05
10
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14.
Typical Avalanche Current vs.Pulsewidth
1000
EAR , Avalanche Energy (mJ)
800
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 75A
600
400
200
0
25
50
75
100
125
150
175
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long as neitherT
jmax
nor Iav (max)
is exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Starting TJ , Junction Temperature (°C)
Fig 15.
Maximum Avalanche Energy vs. Temperature
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