The A4409 is supplied in a low-profile (1.2 mm maximum height),
20-lead eTSSOP package (suffix “LP”) with exposed thermal pad.
Temp. Range
–40°C to 150°C
Package
20-pin eTSSOP with thermal pad
Packing
[1]
4000 pieces per 13-in. reel
Lead Frame
100% Matte Tin
Contact Allegro for additional packing options.
ABSOLUTE MAXIMUM RATINGS
[2]
Characteristic
VIN pin
ENBAT pin
Symbol
V
IN
V
ENBAT
I
ENBAT
LX pin
VCP, CP1, and CP2 pins
All other pins
Junction Temperature
Storage Temperature Range
[2]
Notes
Rating
−0.3 to 40
−0.3 to 8
Unit
V
V
V
mA
V
V
V
V
V
°C
°C
With current limiting resistor
[3]
−13 to 40
±75
−0.3 to V
IN
+ 0.3
V
LX
V
VCP
, V
CPx
T
J
T
S
t < 250 ns
t < 50 ns
−1.5
V
IN
+ 3
−0.3 to 50
−0.3 to 7.5
−40 to 150
−55 to 150
Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
[3]
The higher ENBAT ratings (–13 V and 40 V) are measured at node “A” in the following circuit configuration:
Node “A”
≥450
ENBAT
V
ENBAT
-
+
A4409
GND
THERMAL CHARACTERISTICS
:
May require derating at maximum conditions; see application information
Characteristic
Junction-to-Ambient Thermal
Resistance
[4]
Additional
Symbol
R
θJC
eTSSOP-20 (LP) Package
Test Conditions
[4]
Value
32
Unit
°C/W
thermal information available on the Allegro website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A4409
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with
2 LDOs, Window Watchdog Timer, and NPOR
Table of Contents
Features and Benefits
Description
Applications
Package
Simplified Block Diagram
Selection Guide
Absolute Maximum Ratings
Thermal Characteristics
Functional Block Diagram
Pinout Diagram and Terminal List Table
Electrical Characteristics
1
1
1
1
1
2
2
2
4
5
6
General Specification
6
Buck and Buck-Boost Pre-Regulator Specifications
7
Linear Regulator (LDO) Specifications
9
Control Inputs
10
Diagnostic Outputs
11
Window Watchdog Timer (WWDT)
13
Timing Diagrams
17
Design and Component Selection
Setting Up the Pre-Regulator
Soft Start and Startup
Charge Pump Capacitors
PWM Switching Frequency
Pre-Regulator Output Inductor (L1)
Pre-Regulator Output Capacitors
Ceramic Input Capacitors
Buck-Boost Asynchronous Diode (D1)
Boost MOSFET (Q1)
Boost Diode (D2)
Pre-Regulator Compensation Components
Linear Regulators
Internal Bias (VCC)
Signal Pins (NPOR, ENBAT)
Watchdog (WD
ENn
, WD
IN
, WD
ADJ
)
PCB Layout Guidelines
Pin ESD Structures
Package Outline Drawings
21
21
21
21
21
21
22
22
23
23
23
23
24
24
24
24
27
29
30
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A4409
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with
2 LDOs, Window Watchdog Timer, and NPOR
VBAT
2.2 µF
VCP
CP1
CP2
1 µF
D
IN
VIN
0.1 µF
0603
50-100 µF
50 V
KEY_SW
2 × 4.7 µF
50 V
1210
VCC
1 µF
10 pF
17.4 kΩ
3.3 nF
100 nA
SYNC (optional)
8.66 kΩ
BG1_UV
BG2_UV
VIN_UV
VCP OV
*D1
MISSING
*I
LX(LIM)
MPOR
NPOR
NPOR
CLK
1MHz
NPOR
TIMING
FSET/SYNC
OSC1
COMP
LDO
BG1
VREG
BG1
BG2
EN
BG2
BG1_UV
BG1
VCP
UV/OV
CHARGE
PUMP
0.1 µA
BG2_UV
BG2
COMP
75 mΩ
BUCK-BOOST
PRE-REGULATOR
(VREG)
WITH HICCUP MODE
STOP PWM
LX
L1
6.8 µH
≤ 60 mΩ
TYP
REMOVE D2 AND Q1
FOR BUCK ONLY MODE
D2
BG2
OSC2
CLK
1MHz
CLK @ f
OSC
BG1
VREG ON
VCP UV
6.6 V
250 mA
D1
CONNECT LG TO VCC
FOR BUCK ONLY MODE
FB2
FB1
VREG
1Ω
VLDO
FOLDBACK
Q1
2 kΩ
4 × 10 µF
16 V / X7R / 1206
VREG_OV
LG
MASTER
IC POR
* indicates a
latched fault
SS OK
SOFT START
t
SS
5V0
TSD
2.2 µF
BG1
WD
START
WD
FAULT
5V0 UV
*D1
MISSING
*I
LX(LIM)
BG2
LDOs ON
STARTUP /
SHUTDOWN
SEQUENCE
VREG ON
LDOs ON
BG2
5V0 UV
5V0 UV
5V
LDO
FOLDBACK
5V0
2.2 µF
5V
300 mA
ON
EN
MPOR
5V0 UV
VREG_OK
5V
LDO
V5
2.2 µF
5V
200 mA
DEGLITCH
t
d(FILT)
5V0
3.3 kΩ
ENBAT
650 kΩ
0.1 µF
3.3 V
TYP
2.6 V
TYP
+
–
DEGLITCH
t
d(ENBAT,FILT)
ON
FALLING
DELAY
t
d(off)LDO
EN
WD
ADJ
CLK
IN
WD
ENn
13 kΩ
t
WDTO(SLOW)
= 4 ms
t
WDTO(FAST)
= 0.5 ms
WD
IN
WD
ENn
WD
OSC
WD
CLK
WINDOW
WATCHDOG
TIMER
(WWDT)
GND
PGND
ONE SHOT
t
WD(FAULT)
WD
FAULT
WD
ENn
= 0 or OPEN enables WD
60 kΩ
WD
START
CLK
1MHz
A4409
Functional Block Diagram / Typical Schematic
Buck-Boost Mode (f
OSC
= 2 MHz)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A4409
Adjustable Frequency Buck or Buck-Boost Pre-Regulator with
2 LDOs, Window Watchdog Timer, and NPOR
PINOUT DIAGRAM AND TERMINAL LIST TABLE
VCP
VIN
ENBAT
GND
VCC
COMP
FSET/SYNC
NPOR
WD
ENn
WD
IN
1
2
3
4
5
6
7
8
9
10
PAD
20
19
18
17
16
15
14
13
12
11
CP2
CP1
LX
PGND
LG
VREG
VLDO
WD
ADJ
V5
5V0
Package LP, 20-Pin eTSSOP Pinout Diagram
Terminal List Table
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
–
Name
VCP
VIN
ENBAT
GND
VCC
COMP
FSET/
SYNC
NPOR
WD
ENn
WD
IN
5V0
V5
WD
ADJ
VLDO
VREG
LG
PGND
LX
CP1
CP2
PAD
Input voltage
Ignition-enable input from the key/switch through a 1 kΩ resistor
Ground
Internal voltage regulator bypass capacitor pin
Error amplifier compensation network pin for the buck-boost pre-regulator
Frequency setting and synchronization input
Active low, open-drain regulator fault detection output
Watchdog enable pin: Open/Low – WD is enabled, High – WD is disabled
Watchdog refresh input (rising edge triggered) from a microcontroller or
DSP
5 V, 300 mA regulator output
5 V, 200 mA regulator output
The watchdog window time is programmed by connecting R
ADJ
from this
pin to ground
Input for the LDOs
Feedback pin for VREG output, connect to VREG converter output
capacitors
Boost gate drive output for the buck-boost pre-regulator
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