A5995
DMOS Dual Full-Bridge PWM Motor Driver
FEATURES AND BENEFITS
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40 V output rating
Two 3.2 A DC motor drivers
Synchronous rectification
Internal undervoltage lockout (UVLO)
Thermal shutdown circuitry
Crossover-current protection
Very thin profile QFN package
Overcurrent protection
Low-power sleep mode
3.3 and 5 V compatible logic supply
DESCRIPTION
The A5995 is designed to operate at voltages up to 40 V while driving
two DC motors at currents up to 3.2 A. The A5995 includes a fixed
off-time pulse-width modulation (PWM) regulator for current control.
The DC motors are controlled using standard PHASE and ENABLE
signals. Fast or slow current decay is selected via the MODE pin.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.
Protection features include thermal shutdown with hysteresis,
undervoltage lockout (UVLO), crossover-current and short-circuit
protection. Special power-up sequencing is not required.
The A5995 is supplied in a leadless 6 mm × 6 mm × 0.9 mm, 36-pin QFN
package with exposed power tab for enhanced thermal performance.
The package is lead (Pb) free, with 100% matte-tin leadframe plating.
Package: 36-pin QFN with exposed thermal pad
0.90 mm nominal height (suffix EV)
Not to scale
0.1 µF
50 V
CP1
SLEEPn
0.1 µF
50 V
CP2
VCP
VBB
VBB
OUT1A
OUT1A
100 µF
50 V
0.22 µF
50 V
MODE1
PHASE1
Microcontroller or
Controller Logic
ENABLE1
VREF1
MODE2
PHASE2
ENABLE2
VREF2
A5995
OUT1B
OUT1B
SENSE1
SENSE1
OUT2A
OUT2A
OUT2B
OUT2B
SENSE2
SENSE2
GND
GND
GND
GND
Figure 1:Typical Application Circuit
A5995-DS, Rev. 1
A5995
SELECTION GUIDE
Part Number
A5995GEVSR-T
DMOS Dual Full-Bridge PWM Motor Driver
Packing
6000 pieces per reel
ABSOLUTE MAXIMUM RATINGS
Characteristic
Load Supply Voltage
Output Current*
Logic Input Voltage Range
SENSEx Pin Voltage
VREFx Pin Voltage
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Symbol
V
BB
I
OUT
V
IN
V
SENSEx
V
REFx
T
A
T
J
(max)
T
stg
Range G
Pulsed t
w
< 1 µs
DC motor driver, continuous
Notes
Rating
–0.5 to 40
3.2
–0.3 to 7
0.5
2.5
2.5
–40 to 105
150
–55 to 150
Units
V
A
V
V
V
V
°C
°C
°C
* May be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a
Junction Temperature of 150°C.
THERMAL CHARACTERISTICS:
May require derating at maximum conditions
Characteristic
Package Thermal Resistance
Symbol
R
θJA
Test Conditions
EV package, 4-layer PCB based on JEDEC standard
Min.
27
Units
°C/W
Power Dissipation versus Ambient Temperature
5500
5000
4500
4000
Power Dissipation, P
D
(mW)
3500
3000
2500
2000
1500
1000
500
0
25
50
75
100
125
Temperature (°C)
150
175
EV Package
4-layer PCB
(R
θJA
= 27 ºC/W)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A5995
DMOS Dual Full-Bridge PWM Motor Driver
Functional Block Diagram
0.1 µF
50 V
0.1 µF
50 V
100 µF
50 V
0.22 µF
50 V
VCP
VBB
SLEEPn
OSC
CHARGE
PUMP
V
CP
DMOS Full Bridge 1
MODE1
PHASE1
ENABLE1
CONTROL
LOGIC
GATE
DRIVE
VBB
CP1
CP2
OUT1A
OUT1A
OUT1B
OUT1B
Sense1
VREF1
3
-
PWM Latch
BLANKING
SENSE1
SENSE1
+
V
CP
DMOS Full Bridge 2
R
S1
MODE2
PHASE2
ENABLE2
CONTROL
LOGIC
GATE
DRIVE
OUT2A
OUT2A
OUT2B
OUT2B
Sense2
VREF2
3
GND
GND
GND
GND
+
-
PWM Latch
BLANKING
Sense2
SENSE2
SENSE2
NC
NC
NC
NC
NC
NC
R
S2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A5995
DMOS Dual Full-Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS
1
: Valid at T
A
= 25 °C, V
BB
= 40 V, unless otherwise noted
Characteristics
Load Supply Voltage Range
Output On-Resistance
V
f
, Outputs
Output Leakage
I
DSS
Symbol
V
BB
R
DS(on)
Operating
Source driver, I
OUT
= –1.2 A, T
J
= 25°C
Sink driver, I
OUT
= 1.2 A, T
J
= 25°C
I
OUT
= 1.2 A
Outputs, V
OUT
= 0 to V
BB
I
OUT
= 0 mA, outputs on, f
PWM
= 50 kHz,
duty cycle = 50%
Outputs off
Sleep mode
Output Driver Slew Rate
Control Logic
Logic Input Voltage
Logic Input Current
Input Hysteresis
Sleep Rising Threshold
Sleep Falling Threshold
Sleep Hysteresis
Sleep Input Current
V
IN(1)
V
IN(0)
I
IN
V
hys
V
SLEEPn(r)
V
SLEEPn(f)
V
SLEEPn(hys)
I
SLEEPn
PWM change to source on
Propagation Delay Times
t
pd
PWM change to source off
PWM change to sink on
PWM change to sink off
Crossover Delay
Blank Time (DC motor driver)
VREFx Pin Input Voltage Range
VREFx Pin Reference Input Current
Current Trip-Level Error
Protection Circuits
VBB UVLO Threshold
VBB Hysteresis
Overcurrent Protection Threshold
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
1
For
2
Typical
3
V
ERR
Test Conditions
Min.
8
–
–
–
–20
–
–
–10
50
2
–
Typ.
2
–
250
240
–
–
–
11.7
<1
100
–
–
<1
300
2.7
2.4
325
100
700
–
700
–
425
3.2
–
–
–
7.6
500
–
165
15
Max.
40
300
300
1.2
20
23
14
10
150
–
0.8
20
500
2.95
–
450
150
1000
450
1000
450
1000
4
1.5
±1
5
7.9
600
–
175
–
Units
V
mΩ
mΩ
V
µA
mA
mA
µA
ns
V
V
µA
mV
V
V
mV
µA
ns
ns
ns
ns
ns
µs
V
μA
%
V
mV
A
°C
°C
VBB Supply Current
I
BB
SR
OUT
10% to 90%
V
IN
= 0 to 5 V
–20
150
2.5
–
250
–
550
35
550
35
250
2.5
t
CD
t
BLANK
V
REFx
I
REF
V
ERR
V
UV(VBB)
V
UV(VBB)hys
I
OVP
T
JTSD
T
JTSDhys
Operating
V
REF
= 1.5 V
V
REF
= 1.5 V
V
BB
rising
0
–
–5
7.3
400
3.2
155
–
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
= [(V
REF
/3) – V
SENSE
] / (V
REF
/3).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A5995
DMOS Dual Full-Bridge PWM Motor Driver
DC Control Logic
PHASE
1
1
0
0
X
1
0
X
1
0
ENABLE
1
1
1
1
0
0
0
1
1
1
MODE
1
0
1
0
1
0
0
1
0
0
3 × V
S
> V
REF
false
false
false
false
X
X
X
true
true
true
OUTA
H
H
L
L
L
L
H
L
L
H
OUTB
L
L
H
H
L
H
L
L
H
L
Function
Forward (slow decay SR)
Forward (fast decay SR)
Reverse (slow decay SR)
Reverse (fast decay SR)
Brake (slow decay SR)
Fast decay SR*
Fast decay SR*
OCL chop / slow decay SR
OCL chop / fast decay SR*
OCL chop / fast decay SR*
* To prevent reversal of current during fast decay SR – the outputs will go to the high-impedance state as the current gets near zero.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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