LT1573
Low Dropout
PNP Regulator Driver
FEATURES
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DESCRIPTIO
Low Cost Solution for High Current, Low Dropout
Regulators
Fast Transient Response Needs Much Less
Bulk Capacitance
Latching Overload Protection Minimizes
Heat Sink Size
Precision Output Voltage (1%)
Single Supply Operation: V
IN
= 2.8V to 10V
Small Surface Mount Package
Capable of Very Low Dropout Voltage (<0.2V)
Fixed or Adjustable Outputs
Shutdown
The LT
®
1573 is a regulator driver IC designed to provide
a low cost solution for applications requiring high current,
low dropout and fast transient response. When combined
with an external PNP power transistor, this device pro-
vides load current up to 5A with dropout voltages as low
as 0.35V. The LT1573 circuitry is designed for extremely
fast transient response. This greatly reduces bulk storage
capacitance when the regulator is used in applications
with fast, high current load transients.
To keep cost and complexity low, the LT1573 uses a new
time-delayed latching overcurrent protection technique
that requires no external current sense resistor. Base drive
is limited for instantaneous protection, and a time-delayed
latch protects the regulator from continuous short
circuits.
The LT1573 is available as an adjustable regulator with an
output range of 1.27V to 6.8V and with fixed output
voltages of 2.5V, 2.8V and 3.3V. Output accuracy is better
than 1% to meet the critical regulation requirement of fast
microprocessors. A special 8-pin, fused-lead surface mount
package is used to minimize regulator footprint and pro-
vide adequate heat sinking.
APPLICATIO S
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3.3V to 2.5V Regulators
Microprocessor Power Sources
Post Regulator for Switching Supplies
High Efficiency Linear Regulators
Ultralow Dropout Regulators
Low Voltage Linear Regulators
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
C
C
100pF
FB
LATCH
COMP
V
OUT
V
IN
DRIVE
R
C
1k
+
C
TIME
GND
V
IN
5V
LT1573
SHDN
R
D
24Ω
R
B
50Ω
Q
OUT
MOTOROLA
D45H11
50mV/DIV
V
OUT
3.3V
LOAD
R2
1k
GND
1573 F01
C
IN
100µF
TANT
+
C
OUT1
1µF
CER
×
24
+
C
OUT2
220µF
TANT
R1
1.6k
2.5A/DIV
10µs/DIV
V
OUT
= 1.265V (1 + R1/R2)
FOR T < 45°C, C
OUT1
= 24
×
1µF Y5V CERAMIC SURFACE MOUNT CAPACITORS.
FOR T > 45°C, C
OUT1
= 24
×
1µF X7R CERAMIC SURFACE MOUNT CAPACITORS.
PLACE C
OUT1
IN THE MICROPROCESSOR SOCKET CAVITY
Figure 1. 3.3V, 5A Microprocessor Supply
sn1573 1573fas
U
Transient Response for
0.2A to 5A Output Load Step
1573 F01a
U
U
1
LT1573
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
FB 1
LATCH 2
SHDN 3
GND 4
8
7
6
5
COMP
V
OUT
V
IN
DRIVE
Input Pin Voltage (V
IN
to GND) ............................... 10V
Drive Pin Voltage (V
DRIVE
to GND).......................... 10V
Output Pin Voltage (V
OUT
to GND) .......................... 10V
Shutdown Pin Voltage (V
SHDN
to GND) .................. 10V
Operating Junction Temperature Range
LT1573C ............................................... 0°C to 125°C
LT1573I ............................................ –40°C to 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................ 300°C
ORDER PART
NUMBER
LT1573CS8
LT1573CS8-2.5
LT1573CS8-2.8
LT1573CS8-3.3
LT1573IS8
S8 PART MARKING
157333
1573
157325 1573I
157328
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 125°C,
θ
JA
= 85°C/ W
Consult factory for Military grade parts.
The
●
denotes specifications that apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
IN
= 5V, V
DRIVE
= 3V, unless otherwise noted.
PARAMETER
DC Characteristics
LT1573 Reference Voltage (Adjustable)(Note 2)
I
DRIVE
= 20mA, T
J
= 25°C
5mA < I
DRIVE
< 250mA, 3V < V
IN
< 7V,
1.5V < V
DRIVE
< 7V
LT1573-3.3 Output Voltage (Note 2)
I
DRIVE
= 20mA. T
J
= 25°C
5mA < I
DRIVE
< 250mA, 3.5V < V
IN
< 7V,
1.5V < V
DRIVE
< 7V
LT1573-2.8 Output Voltage (Note 2)
I
DRIVE
= 20mA, T
J
= 25°C
5mA < I
DRIVE
< 250mA, 3V < V
IN
< 7V,
1.5V < V
DRIVE
< 7V
LT1573-2.5 Output Voltage (Note 2)
I
DRIVE
= 20mA, T
J
= 25°C
5mA < I
DRIVE
< 250mA, 3V < V
IN
< 7V,
1.5V < V
DRIVE
< 7V
Line Regulation
LT1573 (V
FB
)
LT1573-3.3 (V
OUT
)
LT1573-2.8 (V
OUT
)
LT1573-2.5 (V
OUT
)
Load Regulation
LT1573 (V
FB
)
LT1573-3.3 (V
OUT
)
LT1573-2.8 (V
OUT
)
LT1573-2.5 (V
OUT
)
FB Pin Bias Current (Adjustable Only)
DRIVE Pin Current
DRIVE Pin Saturation Voltage
SHDN Pin Threshold Voltage
SHDN Pin Current
V
SHDN
= 5V
I
DRIVE
= 20mA, 3V < V
IN
< 7V
I
DRIVE
= 20mA, 3.5V < V
IN
< 7V
I
DRIVE
= 20mA, 3V < V
IN
< 7V
I
DRIVE
= 20mA, 3V < V
IN
< 7V
∆I
DRIVE
= 20mA to 250mA
∆I
DRIVE
= 20mA to 250mA
∆I
DRIVE
= 20mA to 250mA
∆I
DRIVE
= 20mA to 250mA
V
FB
= 1.265V
V
FB
= 1.35V, V
DRIVE
= 7V
V
FB
= 1.15V, V
DRIVE
= 1.5V
I
DRIVE
= 20mA, V
FB
= 1.15V
I
DRIVE
= 250mA, V
FB
= 1.15V
●
●
●
●
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN
1.252
1.225
3.267
3.234
2.772
2.744
2.475
2.450
TYP
1.265
1.265
3.3
3.3
2.8
2.8
2.5
2.5
MAX
1.278
1.305
3.333
3.366
2.828
2.856
2.525
2.550
UNITS
V
V
V
V
V
V
V
V
●
●
●
●
●
●
●
●
●
●
●
●
●
●
0.17
0.34
0.34
0.25
7
18
15
13
0.8
250
440
0.12
0.73
1.0
1.33
200
2
5
4
4
30
40
34
30
5
2
0.3
1.4
1.6
sn1573 1573fas
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U
mV
mV
mV
mV
mV
mV
mV
mV
µA
mA
mA
V
V
V
µA
W
U
U
W W
W
LT1573
The
●
denotes specifications that apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
IN
= 5V, V
DRIVE
= 3V, unless otherwise noted.
PARAMETER
LATCH Pin Latch-Off Threshold Voltage
LATCH Pin Charging Current
LATCH Pin Latching Current
V
IN
– V
OUT
Differential Threshold for Latch Disable
Input Quiescent Current
Minimum Input Voltage for Bias Operation
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2:
Operating conditions are limited by maximum junction
temperature. The regulated feedback or output voltage specification will
V
IN
= 7V
●
●
●
ELECTRICAL CHARACTERISTICS
CONDITIONS
●
MIN
0.8
TYP
1.4
7
0.65
MAX
2.2
UNITS
V
µA
mA
0.4
2.8
0.7
1.7
1.0
3.5
V
mA
V
not apply for all possible combinations of input voltage, drive voltage and
drive current. When operating at maximum drive current, the drive voltage
range must be limited. When operating at maximum input and drive
voltage, the drive current must be limited.
TYPICAL PERFOR A CE CHARACTERISTICS
LT1573 Feedback Pin Voltage
vs Temperature
1.290
1.285
3.40
3.38
3.36
OUTPUT VOLTAGE (V)
3.34
3.32
3.30
3.28
3.26
3.24
3.22
0
25 50 75 100 125 150
TEMPERATURE (°C)
1573 G01
FEEDBACK PIN VOLTAGE (V)
1.280
1.275
1.270
1.265
1.260
1.255
1.250
1.245
1.240
–50 –25
OUTPUT VOLTAGE (V)
LT1573-2.5V Output Voltage
vs Temperature
2.60
2.58
2.5
FEEDBACK PIN CURRENT (µA)
2.54
2.52
2.50
2.48
2.46
2.44
2.42
2.40
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
QUIESCENT CURRENT (mA)
2.56
OUTPUT VOLTAGE (V)
U W
LT1573-3.3V Output Voltage
vs Temperature
2.90
2.88
2.86
2.84
2.82
2.80
2.78
2.76
2.74
2.72
–25
50
25
0
75
TEMPERATURE (°C)
100
125
LT1573-2.8V Output Voltage
vs Temperature
3.20
–50
2.70
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
1573 G02
1573 G03
Feedback Pin Bias Current
vs Temperature
3.0
2.5
2.0
1.5
1.0
0.5
Quiescent Current
vs Temperature
2.0
1.5
1.0
0.5
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1573 G05
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
1573 G06
1573 G04
sn1573 1573fas
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LT1573
TYPICAL PERFOR A CE CHARACTERISTICS
Drive Pin Current vs
Feedback Pin Voltage
450
400
DRIVE PIN CURRENT (mA)
1.0
T
J
= 130°C
T
J
= 25°C
T
J
= –45°C
DRIVE PIN VOLTAGE (V)
350
300
250
200
150
100
50
0
0
0.6
0.5
0.4
0.3
0.2
0.1
0
T
J
= 25°C
T
J
= –45°C
V
IN
– V
OUT
(V)
0.2
0.4
0.6 0.8 1.0 1.2
FEEDBACK PIN VOLTAGE (V)
Latch Pin Latch-Off Threshold vs
Input Voltage
3.0
16
LATCH CHARGING CURRENT (µA)
LATCH PIN LATCH-OFF THRESHOLD (V)
2.5
2.0
1.5
T
J
= 125°C
1.0
0.5
0
T
J
= –45°C
T
J
= 25°C
LATCHING CURRENT (mA)
2
3
4
5
6
INPUT VOLTAGE (V)
Shutdown Voltage Threshold vs
Temperature
1.5
SHUTDOWN THRESHOLD (V)
1.4
SHUTDOWN PIN CURRENT (µA)
1.3
1.2
1.1
1.0
–50 –25
4
U W
1573 G07
Drive Pin Saturation Voltage vs
Drive Pin Current
0.85
0.80
0.75
T
J
= 130°C
0.9
0.8
0.7
Latch-Disable Threshold
(V
IN
– V
OUT
) vs Temperature
0.70
0.65
0.60
0.55
0.50
0.45
V
IN
= 5V
LATCH DISABLED FOR
(V
IN
– V
OUT
) < LATCH DISABLE THRESHOLD
1.4
0
50
150
200
250
100
DRIVE PIN CURRENT (mA)
300
0.40
–50 –25
0
100 125 150
TEMPERATURE (°C)
1573 G09
25
50
75
1573 G08
Latch Charging Current vs
Input Voltage
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
2
3
5
4
6
INPUT VOLTAGE (V)
7
8
1573 G11
Latching Current vs Input Voltage
T
J
= 25°C
T
J
= –45°C
T
J
= 125°C
14
12
10
8
6
4
2
0
T
J
= 125°C
T
J
= 25°C
T
J
= –45°C
7
8
1573 G10
0
2
3
4
5
6
INPUT VOLTAGE (V)
7
8
1573 G12
Shutdown Pin Current vs
Shutdown Pin Voltage
300
250
200
150
T
J
= 125°C
100
50
0
T
J
= –45°C
T
J
= 25°C
0
25 50 75 100 125 150
TEMPERATURE (°C)
1573 G13
0
1
2
3
4
5
6
SHUTDOWN PIN VOLTAGE (V)
7
1573 G14
sn1573 1573fas
LT1573
PI FU CTIO S
FB (Pin 1):
The feedback pin is the inverting input of the
error amplifier. The noninverting input of the error ampli-
fier is internally connected to a 1.265V reference. The error
amplifier will servo the drive to the output transistor, Q
OUT
in Figure 1, to force the voltage at the feedback pin to be
1.265V. Output voltage is set by a resistor divider as
shown in Figure 1. For adjustable devices an external
resistor divider is used to set the output voltage. For fixed
voltage devices the resistor divider is internal and the top
of the resistor divider is connected to the V
OUT
pin.
LATCH (Pin 2):
The LT1573 provides overcurrent protec-
tion with a timed latch-off circuit. The latch-off time out is
triggered when the DRIVE pin is pulled below the satura-
tion voltage of the drive transistor. The saturation voltage
is a function of the drive current and is equal to approxi-
mately 130mV at 20mA rising to 780mV at 250mA (see
typical performance curves). The time out is set by the
latch charging current and the value of a capacitor con-
nected between the LATCH pin and ground. If the
overcurrent condition persists at the end of the timing
cycle the regulator will latch off until either the latch is reset
or power is cycled off and back on. The latch can be reset
by either pulling the SHDN pin high, pulling current out of
the LATCH pin greater than latching current or grounding
the LATCH pin. Exceeding the thermal limit temperature
will trigger the latch with no timing delay. Under normal
condition, the DC voltage at the LATCH pin is zero. When
the system is latched off, the DC voltage at theLATCH pin
is two V
BE
above ground.
SHDN (Pin 3):
The SHDN pin has two functions. It can be
used to turn off the output voltage by disabling the drive to
the output transistor. It can also be used to reset the
current limit latch. The shutdown/reset functions are
activated by applying a voltage > 1.3V to the SHDN pin. The
output voltage will restart as soon as the SHDN pin is
pulled below the shutdown threshold. If the shutdown/
reset function is not used, the pin should be grounded. The
voltage applied to the SHDN pin can be higher than the
input voltage. When the SHDN pin voltage is higher than
2V, the SHDN pin current increases and is limited by an
internal 20k resistor.
GND (Pin 4):
Circuit Ground.
DRIVE (Pin 5):
The DRIVE pin is connected to the collector
of the main drive transistor of the LT1573. This drive
transistor sinks the base current of the external PNP
output transistor. A resistor is normally inserted between
the base of the external PNP output transistor and the
DRIVE pin. This resistor is sized to allow the LT1573 to
sink the appropriate amount of base current for a given
application and to activate the overcurrent latch in a fault
condition.
V
IN
(Pin 6):
This pin provides power to all internal circuitry
of the LT1573 including bias, start-up, thermal limit, error
amplifier and all overcurrent latch circuitry.
V
OUT
(Pin 7):
The V
OUT
pin is the input to comparator C1
shown in Block Diagram. This pin is normally connected
to the output. The comparator C1 is used to disable the
overcurrent latch during start-up when the output transis-
tor is saturated. For fixed voltage devices the top of the
internal resistor divider that sets the output voltage is
connected to this pin.
COMP (Pin 8):
A compensation network is inserted
between the V
OUT
and COMP pins to obtain optimal
transient response. Under normal condition, the DC volt-
age of the COMP pin sits at one V
BE
above ground.
U
U
U
sn1573 1573fas
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NXP MCU
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