RMLV0416E Series
4Mb Advanced LPSRAM (256-kword × 16-bit)
R10DS0205EJ0200
Rev.2.00
2016.1.12
Description
The RMLV0416E Series is a family of 4-Mbit static RAMs organized 262,144-word × 16-bit, fabricated by Renesas’s
high-performance Advanced LPSRAM technologies. The RMLV0416E Series has realized higher density, higher
performance and low power consumption. The RMLV0416E Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It is offered in 44-pin TSOP (II) or 48-ball fine pitch ball grid array.
Features
Single 3V supply: 2.7V to 3.6V
Access time: 45ns (max.)
Current consumption:
──
Standby: 0.4µA (typ.)
Equal access and cycle times
Common data input and output
──
Three state output
Directly TTL compatible
──
All inputs and outputs
Battery backup operation
Orderable part number information
Orderable part number
Access
time
Temperature
range
Package
Shipping container
Tray
400-mil 44pin
plastic TSOP (II)
Embossed tape
45 ns
RMLV0416EGBG-4S2#AC
*
-40 ~ +85°C
48-ball FBGA
with 0.75mm
ball pitch
Tray
RMLV0416EGSB-4S2#AA
*
RMLV0416EGSB-4S2#HA
*
RMLV0416EGBG-4S2#KC
*
Embossed tape
R10DS0205EJ0200 Rev.2.00
2016.1.12
Page 1 of 13
RMLV0416E Series
Pin Arrangement
44pin TSOP (II)
A4
A3
A2
A1
A0
CS1#
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O5
I/O6
I/O7
WE#
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE#
UB#
LB#
I/O15
I/O14
I/O13
I/O12
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
CS2
A8
A9
A10
A11
A12
48-ball FBGA
1
A
LB#
2
OE#
3
A0
4
A1
5
A2
6
CS2
B
I/O8
UB#
A3
A4
CS1#
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
Vss
I/O11
A17
A7
I/O3
Vcc
E
Vcc
I/O12
NC
A16
I/O4
Vss
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE#
I/O7
H
NC
A8
A9
A10
A11
NC
(Top view)
(Top view)
Pin Description
Pin name
V
CC
V
SS
A0 to A17
I/O0 to I/O15
CS1#
CS2
OE#
WE#
LB#
UB#
NC
Power supply
Ground
Address input
Data input/output
Chip select 1
Chip select 2
Output enable
Write enable
Lower byte select
Upper byte select
No connection
Function
R10DS0205EJ0200 Rev.2.00
2016.1.12
Page 2 of 13
RMLV0416E Series
Block Diagram
A1
A2
A3
A4
A6
A8
A13
A14
A15
A16
A17
V
CC
V
SS
Row
Decoder
・
・
・
・
・
Memory Matrix
2,048 x 2,048
I/O0
Input
Data
Control
・
・
Column I/O
Column Decoder
・
・
I/O15
A0
A5 A7 A9 A10 A11 A12
・
・
CS2
CS1#
LB#
UB#
WE#
OE#
Control logic
Operation Table
CS1#
H
X
X
L
L
L
L
L
L
L
Note 1.
CS2
X
L
X
H
H
H
H
H
H
H
H: V
IH
L:V
IL
WE#
X
X
X
H
H
H
L
L
L
H
OE#
X
X
X
L
L
L
X
X
X
H
X: V
IH
or V
IL
UB#
X
X
H
L
H
L
L
H
L
X
LB#
X
X
H
L
L
H
L
L
H
X
I/O0 to I/O7
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
High-Z
High-Z
I/O8 to I/O15
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
High-Z
Operation
Standby
Standby
Standby
Read
Lower byte read
Upper byte read
Write
Lower byte write
Upper byte write
Output disable
R10DS0205EJ0200 Rev.2.00
2016.1.12
Page 3 of 13
RMLV0416E Series
Absolute Maximum Ratings
Parameter
Power supply voltage relative to V
SS
Symbol
V
CC
Value
-0.5 to +4.6
-0.5
*2
to V
CC
+0.3
*3
0.7
-40 to +85
-65 to +150
-40 to +85
unit
V
V
W
°C
°C
°C
Terminal voltage on any pin relative to V
SS
V
T
Power dissipation
P
T
Operation temperature
Topr
Storage temperature range
Tstg
Storage temperature range under bias
Tbias
Note 2. -3.0V for pulse
≤
30ns (full width at half maximum)
3. Maximum voltage is +4.6V.
DC Operating Conditions
Symbol
Supply voltage
V
CC
V
SS
Input high voltage
V
IH
Input low voltage
V
IL
Ambient temperature range
Ta
Note 4. -3.0V for pulse
≤
30ns (full width at half maximum)
Parameter
Min.
2.7
0
2.2
-0.3
-40
Typ.
3.0
0
─
─
─
Max.
3.6
0
V
CC
+0.3
0.6
+85
Unit
V
V
V
V
°C
Note
4
DC Characteristics
Parameter
Input leakage current
Output leakage
current
Operating current
Average operating
current
Symbol
| I
LI
|
| I
LO
|
I
CC
Min.
─
─
─
─
I
CC1
─
─
25
mA
Typ.
─
─
─
─
Max.
1
1
10
20
Unit
A
A
mA
mA
Test conditions
Vin = V
SS
to V
CC
CS1# = V
IH
or CS2 = V
IL
or OE# = V
IH
or WE# = V
IL
or LB# = UB# = V
IH
, V
I/O
= V
SS
to V
CC
CS1# = V
IL
, CS2 = V
IH
, Others = V
IH
/V
IL
,
I
I/O
= 0mA
Cycle = 55ns, duty =100%, I
I/O
= 0mA,
CS1# = V
IL
, CS2 = V
IH
, Others = V
IH
/V
IL
Cycle = 45ns, duty =100%, I
I/O
= 0mA,
CS1# = V
IL
, CS2 = V
IH
, Others = V
IH
/V
IL
Cycle =1s, duty =100%, I
I/O
= 0mA,
CS1#
≤
0.2V, CS2
≥
V
CC
-0.2V,
V
IH
≥
V
CC
-0.2V, V
IL
≤
0.2V
CS2 = V
IL
, Others = V
SS
to V
CC
~+25°C
~+40°C
~+70°C
~+85°C
Vin = V
SS
to V
CC,
(1) CS2
≤
0.2V or
(2) CS1#
≥
V
CC
-0.2V,
CS2
≥
V
CC
-0.2V or
(3) LB# = UB#
≥
V
CC
-0.2V,
CS1#
≤
0.2V, CS2
≥
V
CC
-0.2V
I
CC2
Standby current
Standby current
I
SB
─
─
─
─
0.1
*5
0.4
─
─
─
*5
2.5
0.3
2
3
5
7
mA
mA
A
A
A
A
I
SB1
─
─
─
V
OH
2.4
─
─
V
I
OH
= -1mA
V
OH2
V
CC
-0.2
─
─
V
I
OH
= -0.1mA
Output low voltage
V
OL
─
─
0.4
V
I
OL
= 2mA
V
OL2
─
─
0.2
V
I
OL
= 0.1mA
Note 5. Typical parameter indicates the value for the center of distribution at 3.0V (Ta=25ºC), and not 100% tested.
Output high voltage
Capacitance
(Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = -40 ~ +85°C)
Parameter
Symbol
Min.
Input capacitance
C in
─
Input / output capacitance
C
I/O
─
Note 6. This parameter is sampled and not 100% tested.
Typ.
─
─
Max.
8
10
Unit
pF
pF
Test conditions
Vin =0V
V
I/O
=0V
Note
6
6
R10DS0205EJ0200 Rev.2.00
2016.1.12
Page 4 of 13
RMLV0416E Series
AC Characteristics
Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C)
Input pulse levels: V
IL
= 0.4V, V
IH
= 2.4V
Input rise and fall time: 5ns
Input and output timing reference level: 1.4V
Output load: See figures (Including scope and jig)
I/O
C
L
= 30 pF
1.4V
R
L
= 500
ohm
Read Cycle
Parameter
Read cycle time
Address access time
Chip select access time
Output enable to output valid
Output hold from address change
LB#, UB# access time
Chip select to output in low-Z
LB#, UB# enable to low-Z
Output enable to output in low-Z
Chip deselect to output in high-Z
Symbol
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
OH
t
BA
t
CLZ1
t
CLZ2
t
BLZ
t
OLZ
Min.
45
─
─
─
─
10
─
10
10
5
5
0
0
0
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7,8
7,8
7,8
7,8
7,8,9
7,8,9
7,8,9
7,8,9
Note
45
45
45
22
─
45
─
─
─
─
18
18
18
18
t
CHZ1
t
CHZ2
LB#, UB# disable to high-Z
t
BHZ
Output disable to output in high-Z
t
OHZ
Note 7. This parameter is sampled and not 100% tested.
8. At any given temperature and voltage condition, t
CHZ1
max is less than t
CLZ1
min, t
CHZ2
max is less than t
CLZ2
min, t
BHZ
max is less than t
BLZ
min, and t
OHZ
max is less than t
OLZ
min, for any device.
9. t
CHZ1
, t
CHZ2
, t
BHZ
and t
OHZ
are defined as the time when the I/O pins enter a high-impedance state and are not
referred to the I/O levels.
R10DS0205EJ0200 Rev.2.00
2016.1.12
Page 5 of 13
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