NTD4810N, NVD4810N
Power MOSFET
30 V, 54 A, Single N−Channel, DPAK/IPAK
Features
•
•
•
•
Low R
DS(on)
to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
Applications
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V
(BR)DSS
30 V
R
DS(on)
MAX
10 mW @ 10 V
15.7 mW @ 4.5 V
D
I
D
MAX
54 A
•
CPU Power Delivery
•
DC−DC Converters
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (R
qJA
) (Note 1)
Power Dissipation
(R
qJA
) (Note 1)
Continuous Drain
Current (R
qJA
) (Note 2)
Power Dissipation
(R
qJA
) (Note 2)
Continuous Drain
Current (R
qJC
)
(Note 1)
Power Dissipation
(R
qJC
) (Note 1)
Pulsed Drain Current
t
p
=10ms
T
A
= 25°C
T
A
= 85°C
T
A
= 25°C
T
A
= 25°C
Steady
State
T
A
= 85°C
T
A
= 25°C
T
C
= 25°C
T
C
= 85°C
T
C
= 25°C
T
A
= 25°C
T
A
= 25°C
P
D
I
DM
I
DmaxPkg
T
J
, T
stg
I
S
dV/dt
E
AS
P
D
I
D
P
D
I
D
Symbol
V
DSS
V
GS
I
D
Value
30
"20
12.4
9.6
2.62
9
7
1.4
54
42
50
120
45
−55 to
175
41
6.0
98
W
A
A
°C
A
V/ns
mJ
W
A
W
A
Unit
V
V
A
G
N−Channel
S
4
1 2
3
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
AYWW
48
10NG
2
1 Drain 3
Gate Source
A
= Assembly Location*
Y
= Year
WW
= Work Week
4810N = Device Code
G
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
Current Limited by Package
Operating Junction and Storage Temperature
Source Current (Body Diode)
Drain to Source dV/dt
Single Pulse Drain−to−Source Avalanche
Energy (V
DD
= 24 V, V
GS
= 10 V,
L = 1.0 mH, I
L(pk)
= 14 A, R
G
= 25
W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
1
April, 2017 − Rev. 11
Publication Order Number:
NTD4810N/D
NTD4810N, NVD4810N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Junction−to−Case (Drain)
Junction−to−TAB (Drain)
Junction−to−Ambient − Steady State (Note 1)
Junction−to−Ambient − Steady State (Note 2)
1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
Symbol
R
qJC
R
qJC−TAB
R
qJA
R
qJA
Value
3.0
3.5
57.2
107.3
Unit
°C/W
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Parameter
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
Temperature Coefficient
Zero Gate Voltage Drain Current
V
(BR)DSS
V
(BR)DSS
/T
J
I
DSS
V
GS
= 0 V,
V
DS
= 24 V
T
J
= 25°C
T
J
= 125°C
V
GS
= 0 V, I
D
= 250
mA
30
27
1.0
10
"100
nA
V
mV/°C
mA
Symbol
Test Condition
Min
Typ
Max
Unit
Gate−to−Source Leakage Current
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
I
GSS
V
DS
= 0 V, V
GS
=
"20
V
V
GS
= V
DS
, I
D
= 250
mA
V
GS(TH)
V
GS(TH)
/T
J
R
DS(on)
1.5
5.2
2.5
V
mV/°C
V
GS
= 10 to
11.5 V
V
GS
= 4.5 V
I
D
= 30 A
I
D
= 15 A
I
D
= 30 A
I
D
= 15 A
8.0
7.8
12
11
9.0
10
mW
15.7
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
SWITCHING CHARACTERISTICS
(Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
g
FS
V
DS
= 15 V, I
D
= 10 A
S
C
iss
C
oss
C
rss
Q
G(TOT)
Q
G(TH)
Q
GS
Q
GD
Q
G(TOT)
V
GS
= 11.5 V, V
DS
= 15 V,
I
D
= 30 A
V
GS
= 4.5 V, V
DS
= 15 V,
I
D
= 30 A
V
GS
= 0 V, f = 1.0 MHz,
V
DS
= 12 V
1165
284
154
9.2
1.3
3.3
4.4
21
1350
330
200
11
pF
nC
nC
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
V
GS
= 11.5 V, V
DS
= 15 V,
I
D
= 15 A, R
G
= 3.0
W
V
GS
= 4.5 V, V
DS
= 15 V,
I
D
= 15 A, R
G
= 3.0
W
11.5
20.7
13.8
3.8
7.2
20.7
21.8
2.6
ns
ns
3. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD4810N, NVD4810N
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Parameter
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
V
GS
= 0 V,
I
S
= 30 A
T
J
= 25°C
T
J
= 125°C
0.92
0.79
18.2
V
GS
= 0 V, dIs/dt = 100 A/ms,
I
S
= 30 A
10.6
7.6
8.8
nC
ns
1.2
V
Symbol
Test Condition
Min
Typ
Max
Unit
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Time
PACKAGE PARASITIC VALUES
Source Inductance
Drain Inductance, DPAK
Drain Inductance, IPAK
Gate Inductance
Gate Resistance
t
RR
ta
tb
Q
RR
L
S
L
D
L
D
L
G
R
G
T
A
= 25°C
2.49
0.0164
1.88
3.46
2.4
nH
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
NTD4810N, NVD4810N
TYPICAL PERFORMANCE CURVES
60
I
D
, DRAIN CURRENT (AMPS)
50
40
30
20
10
0
0
1
2
3
4
5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10 V
6V
5V
4.5 V
60
V
DS
≥
10 V
3.8 V
3.6 V
3.4 V
3.2 V
3V
2.8 V
I
D
, DRAIN CURRENT (AMPS)
50
40
30
20
10
0
0
1
2
3
4V
T
J
= 25°C
T
J
= 125°C
T
J
= 25°C
T
J
= −55°C
4
5
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.048
0.043
0.038
0.033
0.028
0.023
0.018
0.013
0.008
0.003
3
4
5
6
7
8
9
10
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
I
D
= 30 A
T
J
= 25°C
0.020
T
J
= 25°C
0.015
V
GS
= 4.5 V
0.010
V
GS
= 11.5 V
0.005
0
10
15
20
25
30
35
40
45
50
55
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2.0
I
D
= 30 A
V
GS
= 10 V
I
DSS
, LEAKAGE (nA)
1.5
10,000
100,000
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
V
GS
= 0 V
T
J
= 175°C
1.0
1000
T
J
= 125°C
100
0.5
0
−50 −25
10
0
25
50
75
100
125
150
175
5
10
15
20
25
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Drain Voltage
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NTD4810N, NVD4810N
TYPICAL PERFORMANCE CURVES
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
2000
12
11
10
9
8
7
6
5
4
3
2
Q
1
Q
2
I
D
= 30 A
0 V < V
GS
< 11.5 V
T
J
= 25°C
V
DS
= 0 V V
GS
= 0 V
C
iss
T
J
= 25°C
Q
T
C, CAPACITANCE (pF)
1500
C
iss
1000
C
rss
500
C
oss
0
10
C
rss
5
V
GS
0
V
DS
5
10
15
20
25
1
0
0 1 2 3 4 5 6 7 8 9 10 111213 141516 171819 202122
Q
G
, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
1000
IS, SOURCE CURRENT (AMPS)
V
DD
= 15 V
I
D
= 30 A
V
GS
= 11.5 V
t, TIME (ns)
100
30
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
V
GS
= 0 V
25
20
15
10
5
0
0.5
T
J
= 25°C
t
d(off)
10
t
r
t
d(on)
t
f
1
1
10
R
G
, GATE RESISTANCE (OHMS)
100
0.6
0.7
0.8
0.9
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
1000
I D, DRAIN CURRENT (AMPS)
110
100
90
80
70
60
50
40
30
20
10
0
25
Figure 10. Diode Forward Voltage vs. Current
I
D
= 14 A
100
10
ms
100
ms
10
1
V
GS
= 20 V
SINGLE PULSE
T
C
= 25°C
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
1 ms
10 ms
dc
0.1
1
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (°C)
175
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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