MC14511B
BCD−To−Seven Segment
Latch/Decoder/Driver
The MC14511B BCD−to−seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4−bit storage latch, an 8421
BCD−to−seven segment decoder, and an output drive capability. Lamp
test (LT), blanking (BI), and latch enable (LE) inputs are used to test the
display, to turn−off or pulse modulate the brightness of the display, and
to store a BCD code, respectively. It can be used with seven−segment
light−emitting diodes (LED), incandescent, fluorescent, gas discharge,
or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
Features
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MARKING
DIAGRAMS
16
PDIP−16
P SUFFIX
CASE 648
16
MC14511BCP
AWLYYWWG
1
1
16
14511BG
AWLYWW
1
16
14511B
AWLYYWWG
•
•
•
•
•
•
•
•
•
•
Low Logic Circuit Power Dissipation
High−Current Sourcing Outputs (Up to 25 mA)
Latch Storage of Code
Blanking Input
Lamp Test Provision
Readout Blanking on all Illegal Input Combinations
Lamp Intensity Modulation Capability
Time Share (Multiplexing) Facility
Supply Voltage Range = 3.0 V to 18 V
Capable of Driving Two Low−power TTL Loads, One Low−power
Schottky TTL Load, or Two HTL Loads Over the Rated Temperature
Range
•
Chip Complexity: 216 FETs or 54 Equivalent Gates
•
Triple Diode Protection on all Inputs
•
Pb−Free Packages are Available*
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 1)
Symbol
V
DD
V
in
I
P
D
T
A
T
stg
I
OHmax
P
OHmax
Parameter
DC Supply Voltage Range
Input Voltage Range, All Inputs
DC Current Drain per Input Pin
Power Dissipation,
per Package (Note 2)
Operating Temperature Range
Storage Temperature Range
Maximum Output Drive Current
(Source) per Output
Maximum Continuous Output Power
(Source) per Output (Note 3)
Value
−0.5
to +18.0
−0.5
to V
DD
+ 0.5
10
500
−55
to +125
−65
to +150
25
50
Unit
V
V
mA
mW
°C
°C
mA
mA
SO−16
D SUFFIX
CASE 751B
SO−16
DW SUFFIX
CASE 751G
1
16
MC14511B
ALYWG
1
SOEIAJ−16
F SUFFIX
CASE 966
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/°C From 65°C to 125°C
3. P
OHmax
= I
OH
(V
DD
−
V
OH
)
©
Semiconductor Components Industries, LLC, 2006
September, 2006
−
Rev. 8
1
Publication Order Number:
MC14511B/D
MC14511B
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages
to this high−impedance circuit. A destructive high current mode may occur if V
in
and V
out
are not constrained to the range
V
SS
v
(V
in
or V
out
)
v
V
DD
.
Due to the sourcing capability of this circuit, damage can occur to the device if V
DD
is applied, and the outputs are shorted
to V
SS
and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
SS
or V
DD
).
PIN ASSIGNMENT
B
C
LT
BI
LE
D
A
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
f
g
a
b
c
d
e
e
d
f
a
g
b
c
DISPLAY
0
1
2
3
4
5
6
7
8
9
TRUTH TABLE
LE BI LT
X X 0
X 0 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
0
1 1
1
1 1
Inputs
D
C
X
X
X
X
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
B
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
A
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
a
1
0
1
0
1
1
0
1
0
1
1
1
0
0
0
0
0
0
b
1
0
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
c
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
d
1
0
1
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
*
Outputs
e
f
1
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
g
1
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
Display
8
Blank
0
1
2
3
4
5
6
7
8
9
Blank
Blank
Blank
Blank
Blank
Blank
*
X = Don’t Care
* Depends upon the BCD code previously applied when LE = 0
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2
MC14511B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
−
55°C
25°C
125°C
Characteristic
Symbol
V
OL
Vdc
Min
−
−
−
4.1
9.1
14.1
−
−
−
3.5
7.0
11
4.1
−
3.9
−
3.4
−
9.1
−
9.0
−
8.6
−
14.1
−
14
−
13.6
−
0.64
1.6
4.2
−
−
−
−
−
Max
Min
−
−
−
4.1
9.1
14.1
−
−
−
3.5
7.0
11
4.1
−
3.9
−
3.4
−
9.1
−
9.0
−
8.6
−
14.1
−
14
−
13.6
−
0.51
1.3
3.4
−
−
−
−
−
Typ
(Note 4)
0
0
0
4.57
9.58
14.59
2.25
4.50
6.75
2.75
5.50
8.25
4.57
4.24
4.12
3.94
3.70
3.54
9.58
9.26
9.17
9.04
8.90
8.70
14.59
14.27
14.18
14.07
13.95
13.70
0.88
2.25
8.8
±
0.00001
5.0
0.005
0.010
0.015
Max
Min
−
−
−
4.1
9.1
14.1
−
−
−
3.5
7.0
11
4.1
−
3.5
−
3.0
−
9.1
−
8.6
−
8.2
−
14.1
−
13.6
−
13.2
−
0.36
0.9
2.4
−
−
−
−
−
Max
Unit
Vdc
Output Voltage
V
in
= V
DD
or 0
V
in
= 0 or V
DD
“0” Level
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
±
0.1
−
5.0
10
20
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
±
0.1
7.5
5.0
10
20
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
±
1.0
−
150
300
600
“1” Level
V
OH
Vdc
Input Voltage #
“0” Level
(V
O
= 3.8 or 0.5 Vdc)
(V
O
= 8.8 or 1.0 Vdc)
(V
O
= 13.8 or 1.5 Vdc)
(V
O
= 0.5 or 3.8 Vdc)
(V
O
= 1.0 or 8.8 Vdc)
(V
O
= 1.5 or 13.8 Vdc)
Output Drive Voltage
(I
OH
= 0 mA)
(I
OH
= 5.0 mA)
(I
OH
= 10 mA)
(I
OH
= 15 mA)
(I
OH
= 20 mA)
(I
OH
= 25 mA)
(I
OH
= 0 mA)
(I
OH
= 5.0 mA)
(I
OH
= 10 mA)
(I
OH
= 15 mA)
(I
OH
= 20 mA)
(I
OH
= 25 mA)
(I
OH
= 0 mA)
(I
OH
= 5.0 mA)
(I
OH
= 10 mA)
(I
OH
= 15 mA)
(I
OH
= 20 mA)
(I
OH
= 25 mA)
Output Drive Current
(V
OL
= 0.4 V)
(V
OL
= 0.5 V)
(V
OL
= 1.5 V)
Input Current
Input Capacitance
Quiescent Current
(Per Package) V
in
= 0 or V
DD
,
I
out
= 0
mA
Total Supply Current (Notes 5 & 6)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
Sink
I
OL
“1” Level
V
IL
Vdc
V
IH
Vdc
Source
V
OH
Vdc
10
Vdc
15
Vdc
5.0
10
15
15
−
5.0
10
15
5.0
10
15
mAdc
I
in
C
in
I
DD
mAdc
pF
mAdc
I
T
I
T
= (1.9
mA/kHz)
f + I
DD
I
T
= (3.8
mA/kHz)
f + I
DD
I
T
= (5.7
mA/kHz)
f + I
DD
mAdc
4. Noise immunity specified for worst−case input combination.
Noise Margin for both “1” and “0” level =
1.0 Vdc min @ V
DD
= 5.0 Vdc
2.0 Vdc min @ V
DD
= 10 Vdc
2.5 Vdc min @ V
DD
= 15 Vdc
5. The formulas given are for the typical characteristics only at 25°C.
6. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + 3.5 x 10
–3
(C
L
– 50) V
DD
f
where: I
T
is in
mA
(per package), C
L
in pF, V
DD
in Vdc, and f in kHz is input frequency.
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3
MC14511B
Input LE low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective C
L
loads.
20 ns
A, B, AND C
90%
50%
1
2f
20 ns
V
DD
10%
V
SS
V
OH
V
OL
50% DUTY CYCLE
ANY OUTPUT
50%
Figure 1. Dynamic Power Dissipation Signal Waveforms
20 ns
20 ns
INPUT C
t
PLH
OUTPUT g
50%
10%
t
TLH
t
THL
V
OL
OUTPUT g
V
OL
90%
50%
10%
t
PHL
90%
20 ns
V
DD
V
SS
V
OH
INPUT C
50%
V
SS
V
OH
90%
50%
t
h
t
su
V
DD
V
DD
V
SS
LE
10%
(a) Inputs D and LE low, and
Inputs A, B, BI and LT high.
(b) Input D low,
Inputs A, B, BI and LT high.
20 ns
LE
90%
50%
10%
t
WL
20 ns
V
DD
V
SS
(c) Data DCBA strobed into latches.
Figure 2. Dynamic Signal Waveforms
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