SMM205
Preliminary Information
1
(See Last Page)
Dual Channel Supply Voltage Marginer and Active DC Output Controller
FEATURES & APPLICATIONS
•
Extremely accurate (±0.1%) Active
DC Output Control (ADOC)
•
ADOC Automatically adjusts supply output
voltage level under all load conditions
•
Capable of margining supplies with trim inputs
using either positive or negative trim pin control
•
Wide Margin/ADOC range from 0.3V to VDD
•
Uses either an internal or external VREF
•
Operates from any intermediate bus supply
from 8V to 15V and from 2.7V to 5.5V
•
Programmable START and READY pins
•
Two programmable general purpose monitor
sensors – UV and OV with FAULT Output Flag
•
General Purpose 1k EEPROM with Write Protect
•
I
2
C 2-wire serial bus for programming
configuration and monitoring status.
•
28 lead QFN package
INTRODUCTION
The SMM205 actively controls the output voltage level
of two DC/DC converters that use a Trim or VADJ/FB
pin to adjust the output. An Active DC Output Control
(ADOC) feature is used during normal operation to
maintain extremely accurate settings of supply
voltages and, during system test, to control margining
of the supplies using I
2
C commands. Total accuracy
with a ±0.1% external reference is ±0.2%, and ±0.5%
using the internal reference. The device can margin
supplies with either positive or negative trim pin control
within a range of 0.3V to VDD. The SMM105 supply
can be from 12V, 8V, 5V or 3.3V to as low as 2.7V to
accommodate any intermediate bus supply.
The voltage settings (margin high/low and nominal)
are programmed into nonvolatile memory through the
industry standard I
2
C 2-wire data bus. The I
2
C bus is
also used to enable margin high, margin low, ADOC or
normal operation. When margining, the SMM205
checks the voltage output of the converter and make
adjustments to the trim pin via a feedback loop to bring
the voltage to the margin setting. A margining status
register is set to indicate that the system is ready for
test. The SMM205 ADOC continues to monitor and
adjust the channel output at the specified level.
Applications
•
In-system test and control of Point-of-Load
(POL) Power Supplies for Multi-voltage
Processors, DSPs and ASICs
•
Enterprise and edge routers, servers, Storage
Area Networks
SIMPLIFIED APPLICATIONS DRAWING
6V to 15V
2.7V to 5.5V
Intermediate
Bus Voltage
(IBA
I
2
C
BUS
12VIN
WP#
SDA
SCL
A0
A1
A2
VDD
FILT_CAP
TRIM_CAPA
TRIM_CAPB
Vin
V+
V1
GND
Processor
DC/DC
V–
Trim
On/Off
VDD_CAP
TRIMA
VMA
UV
Vin
V+
V2
SMM205
External or
Internal
VREF
COMP1
VREF_CNTL
DC/DC
V–
Trim
On/Off
READY
START
FAULT#
TRIMB
VMB
COMP2
OV
Figure 1 – Applications Schematic showing the SMM205 ADOC actively control the DC output level of 2
DC/DC Converters as well as provide margin control. The SMM205 can operate over a wide supply range
Note: This is an applications example only. Some pins, components and values are not shown.
© SUMMIT
Microelectronics, Inc. 2003 •
1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897
2069 1.4 6/23/03
www.summitmicro.com
GND
1
SMM205
Preliminary Information
Figure 2 – Example Power Supply Margining using the SMM205. The waveform on the left is margin nominal
to high from 2.5V to 2.8V and 1.8V to 2.1V. The waveform on the right is margin nominal to low from 2.5V to
2.2V and 1.8V to 1.5V. The bottom waveform is the READY signal indicating when margining is complete.
GENERAL DESCRIPTION
The SMM205 is capable of controlling and margining
the DC output voltage of LDOs or DC/DC converters
that use a trim/adjust pin and to automatically change
the level using a unique Active DC Output Control
(ADOC). The ADOC function is programmable over a
standard 2-wire I
2
C serial data interface and can be
used to set the nominal DC output voltage as well as
the margin high and low settings. The part actively
controls the programmed set levels to maintain tight
control over load variations and voltage drops at the
point of load. The margin range will vary depending on
the supply manufacturer and model but the normal
range is 10% adjustment around the nominal output
setting. However, the SMM205 has the capability to
margin from VREF_CNTL to VDD.
The user can set the desired voltage settings
(nominal, margin high and margin low) into the EE
memory array for the device. Then, volatile registers
are used to select one of these settings. The registers
are accessed over the I
2
C bus.
In normal operation, Active DC Output Control is set to
adjust the nominal output voltage of one or two
trimmed converters. Typical converters have
±2%
accuracy ratings for their output voltage. Using the
Active DC Output Control feature of the SMM205 can
increase the accuracy to
±0.2%.
This high accuracy
control of a converter output voltage is extremely
important in low voltage applications where deviations
in power supply voltage can result in lower system
performance. Active DC Output Control may be
turned off by de-selecting the function in the Control
Select Register. Active DC Output Control can also be
used for margining a supply during system test.
When the SMM205 receives the command to margin
the Active DC Output Control will adjust the supply to
the selected margin voltage. Once the supply has
reached its margined set point the Ready bit in the
status register will set and the READY pin will go
active. If Active DC Control is disabled a margined
supply can return to its nominal voltage by writing to
the margin command register.
In order to obtain maximum accuracy the SMM205
requires an external voltage reference. An external
reference with ±0.1% accuracy will enable an overall
±0.2% accuracy for the device. A configuration option
also exists so that an internal voltage reference can be
used, but with less accuracy. Total accuracy using the
internal reference is ±0.5%. The SMM205 can be
powered from either a 12V or 8V input via an internal
regulator, or the VDD input (Figure 3).
The SMM205 has two additional input pins and one
additional output pin. The input pins, COMP1 and
COMP2, are high impedance inputs, each connected
to a comparator and compared against the
VREF_CNTL input or the internal reference (VREF).
Each comparator can be independently programmed
to monitor for UV or OV. When either of the COMP1
or COMP2 inputs are in fault the open-drain FAULT#
output will be pulled low. A configuration option exists
to disable the FAULT# output during margining.
Programming of the SMM205 is performed over the
industry standard I
2
C 2-wire serial data interface. A
status register is available to read the state of the part,
and a Write Protect (WP#) pin is available to prevent
writing to the configuration registers and EE memory.
Summit Microelectronics, Inc
2069 1.4 6/23/03
2
SMM205
Preliminary Information
INTERNAL BLOCK DIAGRAM
VREF_CNTL
9
MUX
VREF
CMP
OUTPUT
CONTROL
5
READY
11 FAULT#
TRIM
DRIVE A
20
TRIMA
COMP1 19
COMP2
SDA
SCL
A0
A1
A2
START
WP#
12
28
1
6
4
2
3
8
I
2
C
INTER-
FACE
CMP
CMP
18 TRIM_CAPA
16
TRIM
DRIVE B
INPUT VOLTAGE
SENSING AND
SIGNAL
CONDITIONING
EE
CONFIGURATION
REGISTERS
AND MEMORY
TRIMB
15 TRIM_CAPB
14 VMA
17 VMB
VDD
21
VDD_CAP 23
SUPPLY
ARBITRATION
10 FILT_CAP
12VIN 22
3.6V / 5V
REGULATOR
7
GND
Figure 3 –Block Diagram.
PACKAGE AND PIN CONFIGURATION
28 Pin QFN
Top View
SDA
NC
NC
NC
NC
VDD_CAP
12VIN
28 27 26 25 24 23 22
1
2
3
4
5
6
7
8
9 10 11 12 13 14
21
20
19
18
17
16
15
Pin 1
SCL
A2
START
A1
READY
A0
GND
SMM205
VDD
TRIMA
COMP1
TRIM_CAPA
VMB
TRIMB
TRIM_CAPB
Summit Microelectronics, Inc
WP#
VREF_CNTL
FILT_CAP
FAULT#
COMP2
NC
VMA
2069 1.4 6/23/03
3
SMM205
Preliminary Information
PIN DESCRIPTIONS
Pin
Number
28
1
2
4
6
8
10
15, 18
16, 20
14, 17
Pin
Type
DATA
CLK
I
I
I
I
CAP
CAP
O
I
Pin Name
SDA
SCL
A2
A1
A0
WP#
FILT_CAP
TRIM_CAPx
TRIMx
VMx
I
2
C Bi-directional data line.
I
2
C clock input.
The address pins are biased either to VDD_CAP or GND. When
communicating with the SMM205 over the 2-wire bus these pins provide a
mechanism for assigning a unique bus address.
Write Protect active low input. When asserted writes to the configuration
registers and general purpose EE are not allowed.
External capacitor input used to filter the VM inputs.
External capacitor input used for Active Control and margining.
Output voltage used to control and/or margin converter voltages. Connect
to the converter trim input.
Voltage monitor input. Connect to the DC/DC converter positive sense line
or its +Vout pin.
Voltage reference input used for DC output control and margining.
VREF_CNTL can be programmed to output the internal 1.25V reference
voltage. Pin should be left open if using VREF internal.
Power supply of the part.
Ground of the part. The SMM205 ground pin should be connected to the
ground of the device under control or to a star point ground. PCB layout
should take into consideration ground drops.
12V power supply input internally regulated to either 3.6V or 5.5V. When
using the 3.6V internal regulator option the voltage input can be as low as
8V. It can be as high as 15V using the 5.5V internal regulator.
Programmable active high/low input. The START input is used solely for
enabling Active Control and/or margining.
Programmable active high/low open drain output indicates that VM is at its
set point. When programmed as an active high output READY can also be
used as an input. When pulled low it will latch the state of the comparator
inputs.
External capacitor input used to filter the internal supply rail.
COMP1 and COMP2 are high impedance inputs, each connected internally
to a comparator and compared against the VREF_CNTL input. Each
comparator can be independently programmed to monitor for UV or OV.
The monitor level is set externally with a resistive voltage divider.
When either of the COMP1 or COMP2 inputs are in fault the open-drain
FAULT# output will be pulled low. A configuration option exists to disable
the FAULT# output while the device is margining.
No Connect. Leave floating; do not connect anything to the NC pins.
2069 1.4 6/23/03
Pin Description
9
21
7
I
PWR
GND
VREF_CNTL
VDD
GND
22
PWR
12VIN
3
I
START
5
I/O
READY
23
19
12
CAP
I
I
VDD_CAP
COMP1
COMP2
11
13, 24-27
O
NC
FAULT#
NC
Summit Microelectronics, Inc
4
SMM205
Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ......................–55
°
C to 125
°
C
Storage Temperature............................–65
°
C to 150
°
C
Terminal Voltage with Respect to GND:
VDD Supply Voltage .........................–0.3V to 6.0V
12VIN Supply Voltage.....................–0.3V to 15.0V
All Others ............................... –0.3V to V
DD
+ 0.7V
Output Short Circuit Current ............................... 100mA
Lead Solder Temperature (10 secs)……………….300
°
C
Junction Temperature.........................…….....…...150°C
ESD Rating per JEDEC……………………..……..2000V
Latch-Up testing per JEDEC………..……......…
±
100mA
Note - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of the specification is
not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability. Devices are
ESD sensitive. Handling precautions are recommended.
RECOMMENDED OPERATING CONDITIONS
Temperature Range (Industrial) .......... –40
°
C to +85
°
C
(Commercial)............ –5
°
C to +70
°
C
VDD Supply Voltage.................................. 2.7V to 5.5V
12VIN Supply Voltage (1)........................ 8.0V to 14.0V
VIN.............................................................GND to VDD
VOUT.......................................................GND to 15.0V
Package Thermal Resistance (θ
JA
)
28 Lead QFN………………………………….…80
o
C/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
Note (1) — Range depends on internal regulator set to 3.6V or 5.5V,
see 12VIN specification below.
DC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min.
Typ.
Max
Unit
VDD
12VIN
VM
I
DD
I
12VIN
I
TRIM
V
ADOC
V
IH
V
IL
V
OL
OV/UV
V
HYST
Supply Voltage
Supply Voltage
Positive Sense Voltage
Power Supply Current from
VDD
Power Supply Current from
12VIN
TRIM output current
through 100Ω to 1.0V
Margin Control/ADOC
Range
Input High Voltage
Input Low Voltage
Programmable Open Drain
Output (READY)
Monitor Voltage Range
Base DC Hysteresis
Internally regulated to 5.5V
Internally regulated to 3.6V
VM pin
All TRIM pins and 12VIN floating
All TRIM pins and VDD floating
TRIM Sourcing Max Current
TRIM Sinking Max Current
Depends on Trim range of DC-
DC Converter
VDD = 2.7V
VDD = 5.0V
VDD = 2.7V
VDD = 5.0V
ISINK = TBD
COMP1 and COMP2 pins
COMP1 and COMP2 pins,
V
TH
– V
TL
— Note 1
–0.3
3
10
1.5
1.5
VREF_CNTL
2.7
10
6
–0.3
3.3
5.5
15
14
VDD
V
V
V
mA
mA
mA
mA
3
3
5
5
VDD
VDD
VDD
0.1xVDD
0.3xVDD
0.2
VDD
V
V
V
V
V
mV
0.9xVDD
0.7xVDD
Note 1 – The Base DC Hysteresis voltage is measured with a 1.25V external voltage source. The resulting value is determined by subtracting
Threshold Low from Threshold High (V
TH
– V
TL
) while monitoring the FAULT# pin state. Base DC Hysteresis is measured with a 1.25V input. Actual
DC Hysteresis is derived from the equation: (V
IN
/V
REF
)(Base Hysteresis). For example, if V
IN
= 2.5V and V
REF
= 1.25V then Actual DC Hysteresis =
(2.5V/1.25V) (0.003V) = 6mV.
Summit Microelectronics, Inc
2069 1.4 6/23/03
5
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