Programmable FemtoClock
®
NG
ICS83PN161I
Differential-to-3.3V, 2.5V LVPECL Synthesizer
DATA SHEET
General Description
The ICS83PN161i is LVPECL output synthesizer designed for
converting forward-error correction (FEC) clock frequencies in 10
GB Ethernet LAN/WAN transport applications. The device is
optimized for an input frequency of 156.25MHz and supports four
FEC rate conversions: 33/32, 255/237, 255/238 and 235/236. The
conversion rate is pin-selectable and one of four rates are supported
at a time. In the default configuration, an input clock of 156.25MHz is
converted to an output clock of 168.8294492MHz (255/236).
The device uses IDT's fourth Generation of FemtoClock® NG
technology to deliver low phase noise clocks combined with a low
power consumption. The RMS phase jitter at 168.8294492MHz
output frequency is 0.533ps (12kHz-20MHz integration range).
Features
•
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Fourth Generation FemtoClock
®
Next Generation (NG)
technology
Footprint compatible with 5mm x 7mm differential oscillators
10 Gb Ethernet LAN/WAN FEC clock converter
Supports 33/32, 255/237, 255/238, 255/236 rate conversions
Optimized for an input clock frequency of 156.25MHz
One differential LVPECL output pair
CLK, nCLK input pair can accept the following levels: HCSL,
LVDS, LVPECL, LVHSTL and SSTL
Output frequency range: 161.1328125MHz – 168.8294492MHz
VCO range: 2.0GHz – 2.5GHz
Cycle-to-cycle jitter: 18ps (typical)
RMS phase jitter, 12kHz – 20MHz: 0.533ps (typical)
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Frequency Select Table
FSEL[1:0]
00
01
10
1 1 (default)
Input
156.25
156.25
156.25
156.25
Output Frequency
(MHz)
161.1328125
168.1170886
167.4107143
168.8294492
FEC Rate
Pin Assignment
OE
1
10
FSEL1
FSEL0
9
8
V
CC
33/32
255/237
255/238
255/236
V
EE
3
4
nCLK
5
CLK
6
Q
Reserved
2
7
nQ
ICS83PN161I
10-Lead VFQFN
5mm x 7mm x 1mm package body
K Package
Top View
Block Diagram
Q
CLK
nCLK
Pullup/Pulldown
Pulldown
÷P
Phase
Detector
FemtoClock NG
VCO
÷N
nQ
÷M
2
FSEL[1:0]
Pullup
OE
Pullup
ICS83PN161AKI REVISION C JULY 6, 2011
1
©2011 Integrated Device Technology, Inc.
ICS83PN161I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6, 7
8
9
10
Name
OE
Reserved
V
EE
nCLK
CLK
Q, nQ
V
CC
FSEL0
FSEL1
Input
Reserve
Power
Input
Input
Output
Power
Input
Input
Pullup
Pullup
Pullup/
Pulldown
Pulldown
Type
Pullup
Description
Output enable. External pullup required for normal operation.
LVCMOS/LVTTL interface levels.
Reserved pin. Do not connect.
Negative supply pin.
Inverting differential clock input. V
CC
/2 default when left floating
Non-inverting differential clock input.
Differential output pair. LVPECL interface levels.
Power supply pin.
Feedback control inputs. Sets the output divider value to one of four values.
LVCMOS/LVTTL interface levels. See
Frequency Select Table
on page 1.
Feedback control inputs. Sets the output divider value to one of four values.
LVCMOS/LVTTL interface levels. See
Frequency Select Table
on page 1.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
Ω
k
Ω
R
PULLDOWN
Input Pulldown Resistor
Function Table
Table 3. P, M, N Divider Function Table
FSEL[1:0]
00
01
10
1 1 (default)
P Divider
÷2
÷2
÷2
÷2
M Divider
÷28.87500000
÷30.12658228
÷25.71428571
÷25.93220339
N Divider
÷14
÷14
÷12
÷12
Input Frequency (MHz)
156.25
156.25
156.25
156.25
Output Frequency (MHz)
161.1328125
168.1170886
167.4107143
168.8294492
ICS83PN161AKI REVISION C JULY 6, 2011
2
©2011 Integrated Device Technology, Inc.
ICS83PN161I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
3.63V
-0.5V to V
CC
+ 0.5V
50mA
100mA
39.2°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
189
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
182
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
Input Low Voltage
Input High Current
Input Low Current
FSEL[1:0]
FSEL[1:0]
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
ICS83PN161AKI REVISION C JULY 6, 2011
3
©2011 Integrated Device Technology, Inc.
ICS83PN161I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
Table 4D. Differential DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input High Current
CLK, nCLK
CLK
I
IL
Input Low Current
nCLK
V
PP
V
CMR
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
Test Conditions
V
CC
= V
IN
= 3.465V or 2.625V
V
IN
= 0V,
V
CC
= 3.465V or 2.625V
V
IN
= 0V,
V
CC
= 3.465V or 2.625V
-5
-150
0.15
V
EE
1.3
V
CC
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1: Common mode input voltage is defined as the crossing point.
Table 4E. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.8
V
CC
– 1.6
1.0
Units
V
V
V
NOTE 1: Outputs termination with 50Ω to V
CC
– 2V.
ICS83PN161AKI REVISION C JULY 6, 2011
4
©2011 Integrated Device Technology, Inc.
ICS83PN161I Data Sheet
PROGRAMMABLE FEMTOCLOCK
®
NG DIFFERENTIAL-TO-3.3V, 2.5V LVPECL SYNTHESIZER
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
cc
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
MAX
Parameter
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
Output Duty Cycle
161.1328125MHz, Integration Range:
12kHz – 20MHz
20% to 80%
150
49
Test Conditions
Minimum
161.1328125
18
0.533
Typical
Maximum
168.8294492
30
0.69
450
51
Units
MHz
ps
ps
ps
%
tjit(cc)
tjit(Ø)
t
R
/ t
F
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Refer to the Phase Noise plot.
Table 5B. AC Characteristics,
V
cc
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
MAX
Parameter
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
Output Duty Cycle
161.1328125MHz, Integration Range:
12kHz – 20MHz
20% to 80%
100
49
Test Conditions
Minimum
161.1328125
18
0.533
Typical
Maximum
168.8294492
30
0.69
500
51
Units
MHz
ps
ps
ps
%
tjit(cc)
tjit(Ø)
t
R
/ t
F
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Refer to the Phase Noise plot.
ICS83PN161AKI REVISION C JULY 6, 2011
5
©2011 Integrated Device Technology, Inc.
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