Si51218 Data Sheet
Three Output Factory Programmable Clock Generator
The factory programmable Si51218 is a low power, small footprint and frequency flexible
programmable clock generator targeting low power, low cost and high volume consumer
and embedded applications. The device operates from a single crystal or an external
clock source and generates up to 3 outputs from 32.768 kHz to 170 MHz. The device is
factory programmed to provide customized output frequencies and control input such as
power down and output enable.
Applications
• Crystal/XO replacement
• Digital media players
• Portable devices
• DTV/IPTV
KEY FEATURES
• Generates up to 3 LVCMOS clock outputs
from 32.768 kHz to 170 MHz
• Accepts crystal or reference clock input
• 3 to 165 MHz reference clock input
• 8 to 48 MHz crystal input
• Programmable OE input function
XIN/
3
CLKIN
PLL with
Modulation
Control
Buffers,
Dividers,
and
Switch
Matrix
4
CLKOUT1/REFOUT1
(VDD)/OE
XOUT 2
VDDO 8
VDD 1
VSS 5
To Pin 6/7
V-REG
To Core
To Pin 4
Programmable
Configuration
Register
6
CLKOUT2/REFOUT2
(VDDO)/
OE
7 CLKOUT3 (VDDO)
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Si51218 Data Sheet
Feature List
1. Feature List
The Si51218 highlighted features are listed below.
• Generates up to 3 LVCMOS clock outputs from 32.768 kHz
to 170 MHz
• Accepts crystal or reference clock input
• 3 to 165 MHz reference clock input
• 8 to 48 MHz crystal input
• Programmable OE input function
• Low power dissipation
• Separate voltage supply pins
• V
DD
= 2.5 to 3.3 V
• V
DDO
= 1.8 to 3.3 V (V
DDO
< V
DD
)
• Low cycle-cycle jitter
• Ultra small 8-pin TDFN package (1.4 mm x 1.6 mm)
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Si51218 Data Sheet
Design Considerations
2. Design Considerations
2.1 Typical Application Schematic
2.2 Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1 μF must be used between VDD and VSS on pins 1 and 8. Place the capacitor on
the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept
as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. In addition, a 10 µF capacitor should be
placed between VDD and VSS.
Crystal and Crystal Load:
Only use a parallel resonant fundamental AT cut crystal. Do not use higher overtone crystals. To meet the
crystal initial accuracy specification (in ppm) make sure that the external crystal load capacitor is matched to the crystal load specifica-
tion. To determine the value of CL1 and CL2, use the following formula:
CL1 = CL2 = 2CL − (Cpin + Cp);
where CL is the load capacitance stated by the crystal manufacturer,
Cpin is the Si51218 pin capacitance (3 pF), and
Cp is the parasitic capacitance of the PCB traces.
Example:
If a crystal with CL = 12 pF specification is used and Cp = 1 pF (parasitic PCB capacitance on PCB), 19 pF external capaci-
tors from pins XIN (pin 3) and XOUT (Pin 2) to VSS are required. Users must verify Cp value.
Table 2.1. Crystal Specifications
Equivalent Series Resistance (ESR)
< 50 Ω
Crystal Output Capacitance (CO)
< 3 pF
Load Capacitance (CL)
< 13 pF
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Si51218 Data Sheet
Electrical Specifications
3. Electrical Specifications
Table 3.1. DC Electrical Specifications
(V
DD
= 2.5 V ±10%, or V
DD
= 3.3V ±-10%, V
DDO
= V
DD
, C
L
= 10 pF, T
A
= –40 to 85 °C)
Parameter
Operating Voltage
Symbol
V
DD
Test Condition
V
DD
= 3.3 V ± 10%
V
DD
= 2.5 V ± 10%
V
DDO
Output High Voltage
V
OH
V
DDO
< V
DD
I
OH
= –4 mA
V
DDX
= V
DD
or V
DDO
Output Low Voltage
Input High Voltage
Input Low Voltage
Operating Supply Current
1
V
OL
V
IH
V
IL
I
DD
I
OL
= 4 mA
CMOS Level
CMOS Level
F
IN
= 20 MHz, CLKOUT1 = 32.768
kHz, REFOUT2 = 20 MHz,
CLKOUT3 = 26 MHz, C
L
= 5 pF,
V
DD
= V
DDO
= 3.3 V
Min
2.97
2.25
1.71
V
DDX
–
0.5
—
0.7 V
DD
—
—
Typ
3.3
2.5
—
—
Max
3.63
2.75
3.6
—
Unit
V
V
V
V
—
—
—
7.6
0.3
—
0.3 V
DD
9
V
V
V
mA
Nominal Output Impedance
Internal Pull-up/Pull-down Resistor
Input Pin Capacitance
Load Capacitance
Note:
Z
O
R
PUP
/R
PD
C
IN
C
L
Pin 6
Input pin capacitance
—
—
—
—
30
150k
3
—
—
—
5
10
Ω
Ω
pF
pF
1. I
DD
depends on input and output frequency configurations.
Table 3.2. AC Electrical Specifications
(V
DD
= 2.5 V ±10%, or V
DD
= 3.3 V ±10%, V
DDO
= V
DD
, C
L
= 10 pF, T
A
= –40 to 85 °C)
Parameter
Input Frequency Range
Input Frequency Range
Output Frequency Range
Frequency Accuracy
Output Duty Cycle
Symbol
F
IN1
F
IN2
F
OUT
F
ACC
DC
OUT
Condition
Crystal input
Reference clock Input
Min
8
3
Typ
—
—
—
0
50
Max
48
165
170
—
55
Unit
MHz
MHz
MHz
ppm
%
CLKOUT1: 32.768 kHz to 170 MHz 0.032768
CLKOUT2/3: 3 MHz to 170 MHz
Configuration dependent
Measured at V
DDO
/2
F
OUT
< 75 MHz
Measured at V
DDO
/2
F
OUT
> 75 MHz
40
—
45
50
60
%
Input Duty Cycle
DC
IN
CLKIN, CLKOUT through PLL
30
50
70
%
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Si51218 Data Sheet
Electrical Specifications
Parameter
Output Rise/Fall Time
Period Jitter
Symbol
t
r
/t
f
PJ
1
PJ
2
PJ
3
Cycle-to-Cycle Jitter
CCJ
1
CCJ
2
Power-up Time
Output Enable Time
t
PU
t
OE
Condition
C
L
= 10 pF, 20 to 80%
CLKOUT1/2/3, at the same fre-
quency
CLKOUT1/2/3, at different output
frequencies
1
CLKOUT1/3 at 32.768 kHz, V
DD
=
V
DDO
= 3.3 V
CLKOUT1/2/3, at the same fre-
quency
CLKOUT1/2/3, at different output
frequencies
1
Time from 0.9 V
DD
to valid
frequencies at all clock outputs
Time from OE rising edge to active
at outputs SSCLK1/2 (asynchro-
nous), F
OUT
= 133 MHz
Time from OE falling edge to active
at outputs SSCLK1/2 (asynchro-
nous), F
OUT
= 133 MHz
—
—
—
—
Min
—
—
—
Typ
1
12
30
1500
2
85
145
1.2
15
150
290
2
5
—
Max
2
20
95
2
Unit
ns
ps rms
ps rms
ps
ps
ps
ms
ns
Output Disable Time
t
OD
—
15
—
ns
Note:
1. Example frequency configurations:
• 8 MHz, 100 MHz, 75 MHz
• 48 MHz, 100 MHz, 66 2/3 MHz
• 96 MHz, 133 1/3 MHz, 133 1/3 MHz
2. Jitter performance depends on configuration and programming parameters.
Table 3.3. Absolute Maximum Conditions
Parameter
Main Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Temperature, Soldering
ESD Protection (Human Body Mod-
el)
ESD Protection (Charge Device
Model)
ESD Protection (Machine Model)
Note:
1. While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power
supply sequencing is not required.
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Symbol
V
DD_3.3V
V
IN
T
S
T
A
T
J
T
Sol
ESD
HBM
ESD
CDM
ESD
MM
Condition
Min
–0.5
Typ
—
—
—
—
—
—
—
—
—
Max
4.2
V
DD
+0.5
150
85
125
260
4000
1500
200
Unit
V
V
°C
°C
°C
°C
V
V
V
Relative to V
SS
Non-functional
Functional, I-Grade
Functional, power is applied
Non-functional
JEDEC (JESD 22-A114)
JEDEC (JESD 22-C101)
JEDEC (JESD 22-A115)
–0.5
–65
–40
—
—
–4000
–1500
–200
嵌入式系统
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