Measured from the time VDD reaches 90% of its final value
Measured from the time ST pin crosses 50% threshold
Measured from the time ST pin crosses 50% threshold
f = 6.144 MHz, Vdd = 1.8V
f = 6.144 MHz, Vdd = 2.25V to 3.63V
f = 6.144 MHz, Vdd = 1.8V,
Integration bandwidth = 100 Hz to 40 kHz
[2]
f = 6.144 MHz, Vdd = 2.25V to 3.63V,
Integration bandwidth = 100 Hz to 40 kHz
[2]
Startup, Standby and Resume Timing
T_start
T_stdby
T_resume
T_jitt
T_phj
–
–
–
–
–
RMS Phase Jitter
[3]
RMS Period Jitter
–
–
Notes:
1. Current consumption with load is a function of the output frequency and output load. For any given output frequency, the capacitive loading will increase
current consumption equal to C_load*VDD*f(MHz).
2. Max spec inclusive of 25 mV peak-to-peak sinusoidal noise on VDD. Noise frequency 100 Hz to 20 MHz.
3. Refer to the performance plot section for typical values at 2.5, 2.8, 3.0 and 3.3V condition
Table 2. Pin Description
Pin
1
2
3
4
Symbol
ST
OUT
VDD
GND
Input
Output
Power
Power
Functionality
L: Specified frequency output
H: Output is low (weak pull down). Device goes to the standby mode.
Supply current reduces to I_std.
LVCMOS clock output
Supply voltage. Bypass with a 0.01µF X7R capacitor.
Connect to ground
Top View
ST
1
4
GND
OUT
2
3
VDD
Figure 1. Pin Assignments
Rev 1.2
Page 2 of 10
www.sitime.com
SiT8021
1 to 26 MHz, Ultra-Small µPower Oscillator
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Continuous Power Supply Voltage Range (VDD)
Short Duration Maximum Power Supply Voltage (VDD)
Continuous Maximum Operating Temperature
Short Duration Maximum Operating Temperature
Human Body Model (HBM) ESD Protection
Charge-Device Model (CDM) ESD Protection
Machine Model (MM) ESD Protection
Latch-up Tolerance
Mechanical Shock Resistance
Mechanical Vibration Resistance
1508 CSP Junction Temperature
Storage Temperature
Soldering Temperature (follow standard Pb free soldering guidelines)
–
MII 883, Method 2002
MII 883, Method 2007
≤30 seconds
JESD22-A115
JESD22-C101
T
A
= 25°C
JESD78 Compliant
10,000
70
150
-65 to 150
260
g
g
°C
°C
°C
<30 seconds
Test Condition
Value
-0.5 to 3.63
4.0
105
125
2000
750
200
Unit
V
V
°C
°C
V
V
V
Rev 1.2
Page 3 of 10
www.sitime.com
SiT8021
1 to 26 MHz, Ultra-Small µPower Oscillator
Block Diagram
Figure 2. SiT8021 Block Diagram
Device Operating Modes and Outputs
The SiT8021 supports a ≤0.7 µA standby mode for battery-
powered and other power sensitive applications. The
switching between the active and standby modes is
controlled by the logic level on the ST pin as shown in the
table below.
Output During Startup and Resume
The SiT8021 starts up with the output disabled. The output is
enabled once all internal circuit blocks are active, and logic
LOW or FLOAT is detected on the ST pin.
As shown in Table 4, logic HIGH at the ST pin forces the
SiT8021 into the “standby” state, causing the output to disable.
Upon pulling the ST pin LOW, the device enters the “resume”
state, keeping the output disabled. Once the “resume” state
ends, the device output enables.
The first clock pulse after startup or resume is accurate to the
rated stability.
Table 4. Operating Modes and Output States
ST Pin
LOW
FLOAT
MODE
Active
Active
with 200 kΩ
internal pull-down
Standby
OUTPUT
Specified
frequency
Specified
frequency
Hi-Z,
pulled-down with
1 MΩ impedence
IDD Example
60 µA @ 3.072 MHz
60 µA @ 3.072 MHz
Low Power Design Guidelines
1.3 µA
HIGH
For high EM noise environments, we recommend the following
design guidelines:
Active Mode
The SiT8021 operates in the active mode when the ST pin
is at logic LOW or FLOAT. In the active mode, the device
uses the on-chip frequency synthesizer to generate an
output from the internal MEMS resonator reference. The
frequency of the output is factory programmed based on
the device ordering code.
Place oscillator as far away from EM noise sources as
possible (e.g., high-voltage switching regulators, motor
drive control).
Route noisy PCB traces, such as digital data lines or high
di/dt power supply lines, away from the SiTime oscillator.
Place a solid GND plane underneath the SiTime oscillator
to shield the oscillator from noisy traces on the other
board layers.
Standby Mode
The SiT8021 operates in the standby mode when the ST
pin is at logic HIGH. In the standby mode, all internal
circuits with the exception of the MEMS oscillator circuit
and the ST pin detection logic are turned off to reduce
power consumption. While in standby mode, the input
impedance of the ST pin is increased to further reduce
system-level power consumption.
The output driver of the device in the standby mode is
pulled-down with 1 MΩ impedance.
Manufacturing Guidelines
No Ultrasonic or Megasonic Cleaning: Do not subject the
SiT8021 to an ultrasonic or megasonic cleaning
environment. Permanent damage or long-term reliability
issues to the device may occur in such an event.
Applying board-level underfill (BLUF) to the device is
acceptable, but will cause a slight shift of few ppm in the
initial frequency tolerance. Tested with UF3810, UF3808,
and FP4530 underfill.
Reflow profile, per JESD22-A113D.
For additional manufacturing guidelines and marking/
tape-reel instructions, click on the following link:
sitime.com/component/docman/doc_download/243-
manufactuing-notes-for-sitime-oscillators
Rev 1.2
Page 4 of 10
www.sitime.com
SiT8021
1 to 26 MHz, Ultra-Small µPower Oscillator
Test Circuit and Waveform
tr
80% Vdd
50%
15pF
(including probe
and fixture
capacitance)
Test
Point
VDD
Power
Supply
OUT
tf
20% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
0.01µF
GND
ST
Figure 3. Test Circuit
Note:
4.
Figure 4. Waveform
[4]
Duty Cycle is computed as Duty Cycle = TH/Period.
Timing Diagram
Vdd
ST - Pin 1 Voltage
Min. Operating Voltage
Vdd
VDD - Pin 4 Voltage
NO Glitch first cycle
50% Vdd
T_start
CLK Output
T_resume
CLK Output
T_start: Time to valid clock output from power on
T_resume: Time to valid clock output from the
time ST pin crosses 50% threshold
Figure 5. Startup Timing
[5, 6]
Figure 6. Resume Timing
[5, 6]
Vdd
50% Vdd
ST – Pin 1 Voltage
CLK Output
T_Stdby
HiZ
T_Stdby: Time for output to go high-Z from the time
ST pin crosses 50% threshold
Figure 7. Standby Timing
[5]
Notes:
5. SiT8021 supports “no runt” pulses and “no glitch” output during startup or resume.
6. SiT8021 supports gated output which is accurate within rated frequency stability from the first cycle.
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