c. See Solder Profile (www.vishay.com/ppg?73257). The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not
plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required
to ensure adequate bottom side solder interconnection.
d. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
e. Package limited.
Document Number: 73321
S-83054-Rev. C, 29-Dec-08
www.vishay.com
1
Si5499DC
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
a, b
Maximum Junction-to-Foot (Drain)
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. Maximum under Steady State conditions is 95 °C/W.
t
≤
5s
Steady State
Symbol
R
thJA
R
thJF
Typical
48
17
Maximum
50
20
Unit
°C/W
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Drain-Source Breakdown Voltage
V
DS
Temperature Coefficient
V
GS(th)
Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
V
DS
ΔV
DS
/T
J
ΔV
GS(th)
/T
J
V
GS(th)
I
GSS
I
DSS
I
D(on)
V
GS
= 0 V, I
D
= - 250 µA
I
D
= - 250 µA
V
DS
= V
GS
, I
D
= - 250 µA
V
DS
= V
GS
, I
D
= - 5 mA
V
DS
= 0 V, V
GS
= ± 5 V
V
DS
= - 8 V, V
GS
= 0 V
V
DS
= - 8 V, V
GS
= 0 V, T
J
= 55 °C
V
DS
≤
5 V, V
GS
= - 4.5 V
V
GS
= - 4.5 V, I
D
= - 5.1 A
Drain-Source On-State Resistance
a
R
DS(on)
V
GS
= - 2.5 V, I
D
= - 4.6 A
V
GS
= - 1.8 V, I
D
= - 4.3 A
V
GS
= - 1.5 V, I
D
= - 1.3 A
Forward Transconductance
a
Dynamic
b
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
R
g
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
V
DD
= - 4 V, R
L
= 0.7
Ω
I
D
≅
- 5.6 A, V
GEN
= - 8 V, R
g
= 1
Ω
V
DD
= - 4 V, R
L
= 0.7
Ω
I
D
≅
- 5.6 A, V
GEN
= - 4.5 V, R
g
= 1
Ω
f = 1 MHz
V
DS
= - 4 V, V
GS
= - 8 V, I
D
= - 6 A
V
DS
= - 4 V, V
GS
= - 4.5 V, I
D
= - 6 A
V
DS
= - 4 V, V
GS
= 0 V, f = 1 MHz
1290
420
270
23
14
1.7
2.7
8
10
70
60
30
8
70
55
55
15
110
90
45
15
110
85
85
ns
Ω
35
21
nC
pF
g
fs
V
DS
= - 4 V, I
D
= - 5.1 A
- 25
0.030
0.037
0.046
0.057
18
0.036
0.045
0.056
0.077
S
Ω
- 0.35
- 0.55
± 100
-1
- 10
-8
6
2.3
- 0.8
V
mV/°C
V
nA
µA
A
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
www.vishay.com
2
Document Number: 73321
S-83054-Rev. C, 29-Dec-08
Si5499DC
Vishay Siliconix
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current
Body Diode Voltage
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
Reverse Recovery Rise Time
I
S
I
SM
V
SD
t
rr
Q
rr
t
a
t
b
I
F
= - 5.6 A, dI/dt = 100 A/µs, T
J
= 25 °C
I
S
= - 2.1 A, V
GS
= 0 V
- 0.7
45
18
18
17
T
C
= 25 °C
-6
- 25
- 1.2
70
27
A
V
ns
nC
ns
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Notes:
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
